e8082a28c8
once a ST is sent off, it's OK to keep processing, however it's a little more complicated to handle the packet acknowledging the store is completed
1325 lines
42 KiB
C++
1325 lines
42 KiB
C++
/*
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* Copyright (c) 2007 MIPS Technologies, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Korey Sewell
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*
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*/
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#include <list>
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#include <vector>
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#include "arch/isa_traits.hh"
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#include "arch/locked_mem.hh"
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#include "arch/predecoder.hh"
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#include "arch/utility.hh"
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#include "config/the_isa.hh"
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#include "cpu/inorder/resources/cache_unit.hh"
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#include "cpu/inorder/cpu.hh"
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#include "cpu/inorder/pipeline_traits.hh"
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#include "cpu/inorder/resource_pool.hh"
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#include "debug/Activity.hh"
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#include "debug/AddrDep.hh"
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#include "debug/InOrderCachePort.hh"
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#include "debug/InOrderStall.hh"
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#include "debug/InOrderTLB.hh"
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#include "debug/LLSC.hh"
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#include "debug/RefCount.hh"
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#include "debug/ThreadModel.hh"
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#include "mem/request.hh"
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using namespace std;
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using namespace TheISA;
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using namespace ThePipeline;
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#if TRACING_ON
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static std::string
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printMemData(uint8_t *data, unsigned size)
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{
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std::stringstream dataStr;
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for (unsigned pos = 0; pos < size; pos++) {
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ccprintf(dataStr, "%02x", data[pos]);
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}
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return dataStr.str();
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}
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#endif
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Tick
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CacheUnit::CachePort::recvAtomic(PacketPtr pkt)
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{
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panic("CacheUnit::CachePort doesn't expect recvAtomic callback!");
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return curTick();
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}
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void
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CacheUnit::CachePort::recvFunctional(PacketPtr pkt)
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{
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panic("CacheUnit::CachePort doesn't expect recvFunctional callback!");
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}
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void
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CacheUnit::CachePort::recvStatusChange(Status status)
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{
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if (status == RangeChange)
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return;
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panic("CacheUnit::CachePort doesn't expect recvStatusChange callback!");
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}
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bool
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CacheUnit::CachePort::recvTiming(Packet *pkt)
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{
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cachePortUnit->processCacheCompletion(pkt);
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return true;
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}
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void
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CacheUnit::CachePort::recvRetry()
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{
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cachePortUnit->recvRetry();
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}
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CacheUnit::CacheUnit(string res_name, int res_id, int res_width,
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int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params)
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: Resource(res_name, res_id, res_width, res_latency, _cpu),
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cachePortBlocked(false)
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{
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cachePort = new CachePort(this);
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// Hard-Code Selection For Now
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if (res_name == "icache_port")
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_tlb = params->itb;
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else if (res_name == "dcache_port")
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_tlb = params->dtb;
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else
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fatal("Unrecognized TLB name passed by user");
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for (int i=0; i < MaxThreads; i++) {
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tlbBlocked[i] = false;
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}
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}
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TheISA::TLB*
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CacheUnit::tlb()
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{
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return _tlb;
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}
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Port *
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CacheUnit::getPort(const string &if_name, int idx)
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{
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if (if_name == resName)
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return cachePort;
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else
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return NULL;
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}
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void
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CacheUnit::init()
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{
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for (int i = 0; i < width; i++) {
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reqs[i] = new CacheRequest(this);
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}
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// Currently Used to Model TLB Latency. Eventually
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// Switch to Timing TLB translations.
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resourceEvent = new CacheUnitEvent[width];
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cacheBlkSize = this->cachePort->peerBlockSize();
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cacheBlkMask = cacheBlkSize - 1;
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initSlots();
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}
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int
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CacheUnit::getSlot(DynInstPtr inst)
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{
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ThreadID tid = inst->readTid();
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if (tlbBlocked[inst->threadNumber]) {
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return -1;
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}
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// For a Split-Load, the instruction would have processed once already
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// causing the address to be unset.
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if (!inst->validMemAddr() && !inst->splitInst) {
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panic("[tid:%i][sn:%i] Mem. Addr. must be set before requesting "
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"cache access\n", inst->readTid(), inst->seqNum);
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}
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Addr req_addr = inst->getMemAddr();
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if (resName == "icache_port" ||
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find(addrList[tid].begin(), addrList[tid].end(), req_addr) ==
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addrList[tid].end()) {
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int new_slot = Resource::getSlot(inst);
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if (new_slot == -1)
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return -1;
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inst->memTime = curTick();
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setAddrDependency(inst);
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return new_slot;
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} else {
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// Allow same instruction multiple accesses to same address
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// should only happen maybe after a squashed inst. needs to replay
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if (addrMap[tid][req_addr] == inst->seqNum) {
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int new_slot = Resource::getSlot(inst);
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if (new_slot == -1)
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return -1;
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return new_slot;
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} else {
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DPRINTF(InOrderCachePort,
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"[tid:%i] Denying request because there is an outstanding"
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" request to/for addr. %08p. by [sn:%i] @ tick %i\n",
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inst->readTid(), req_addr, addrMap[tid][req_addr], inst->memTime);
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return -1;
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}
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}
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return -1;
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}
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void
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CacheUnit::setAddrDependency(DynInstPtr inst)
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{
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Addr req_addr = inst->getMemAddr();
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ThreadID tid = inst->readTid();
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addrList[tid].push_back(req_addr);
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addrMap[tid][req_addr] = inst->seqNum;
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DPRINTF(AddrDep,
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"[tid:%i]: [sn:%i]: Address %08p added to dependency list (size=%i)\n",
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inst->readTid(), inst->seqNum, req_addr, addrList[tid].size());
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//@NOTE: 10 is an arbitrarily "high" number, but to be exact
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// we would need to know the # of outstanding accesses
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// a priori. Information like fetch width, stage width,
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// fetch buffer, and the branch resolution stage would be
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// useful for the icache_port. For the dcache port, the #
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// of outstanding cache accesses (mshrs) would be a good
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// sanity check here.
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//assert(addrList[tid].size() < 10);
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}
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void
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CacheUnit::removeAddrDependency(DynInstPtr inst)
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{
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ThreadID tid = inst->readTid();
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Addr mem_addr = inst->getMemAddr();
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inst->unsetMemAddr();
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// Erase from Address List
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std::list<Addr>::iterator list_it = find(addrList[tid].begin(),
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addrList[tid].end(),
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mem_addr);
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assert(list_it != addrList[tid].end() || inst->splitInst);
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if (list_it != addrList[tid].end()) {
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DPRINTF(AddrDep,
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"[tid:%i]: [sn:%i] Address %08p removed from dependency "
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"list\n", inst->readTid(), inst->seqNum, (*list_it));
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addrList[tid].erase(list_it);
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// Erase From Address Map (Used for Debugging)
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addrMap[tid].erase(addrMap[tid].find(mem_addr));
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}
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}
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ResReqPtr
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CacheUnit::findRequest(DynInstPtr inst)
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{
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for (int i = 0; i < width; i++) {
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CacheRequest* cache_req =
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dynamic_cast<CacheRequest*>(reqs[i]);
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assert(cache_req);
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if (cache_req->valid &&
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cache_req->getInst() == inst &&
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cache_req->instIdx == inst->curSkedEntry->idx) {
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return cache_req;
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}
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}
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return NULL;
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}
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ResReqPtr
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CacheUnit::findRequest(DynInstPtr inst, int idx)
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{
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for (int i = 0; i < width; i++) {
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CacheRequest* cache_req =
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dynamic_cast<CacheRequest*>(reqs[i]);
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assert(cache_req);
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if (cache_req->valid &&
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cache_req->getInst() == inst &&
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cache_req->instIdx == idx) {
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return cache_req;
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}
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}
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return NULL;
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}
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ResReqPtr
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CacheUnit::getRequest(DynInstPtr inst, int stage_num, int res_idx,
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int slot_num, unsigned cmd)
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{
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ScheduleEntry* sched_entry = *inst->curSkedEntry;
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CacheRequest* cache_req = dynamic_cast<CacheRequest*>(reqs[slot_num]);
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if (!inst->validMemAddr()) {
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panic("Mem. Addr. must be set before requesting cache access\n");
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}
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MemCmd::Command pkt_cmd;
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switch (sched_entry->cmd)
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{
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case InitSecondSplitRead:
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pkt_cmd = MemCmd::ReadReq;
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DPRINTF(InOrderCachePort,
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"[tid:%i]: Read request from [sn:%i] for addr %08p\n",
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inst->readTid(), inst->seqNum, inst->split2ndAddr);
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break;
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case InitiateReadData:
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pkt_cmd = MemCmd::ReadReq;
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DPRINTF(InOrderCachePort,
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"[tid:%i]: Read request from [sn:%i] for addr %08p\n",
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inst->readTid(), inst->seqNum, inst->getMemAddr());
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break;
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case InitSecondSplitWrite:
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pkt_cmd = MemCmd::WriteReq;
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DPRINTF(InOrderCachePort,
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"[tid:%i]: Write request from [sn:%i] for addr %08p\n",
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inst->readTid(), inst->seqNum, inst->split2ndAddr);
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break;
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case InitiateWriteData:
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pkt_cmd = MemCmd::WriteReq;
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DPRINTF(InOrderCachePort,
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"[tid:%i]: Write request from [sn:%i] for addr %08p\n",
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inst->readTid(), inst->seqNum, inst->getMemAddr());
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break;
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default:
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panic("%i: Unexpected request type (%i) to %s", curTick(),
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sched_entry->cmd, name());
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}
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cache_req->setRequest(inst, stage_num, id, slot_num,
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sched_entry->cmd, pkt_cmd,
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inst->curSkedEntry->idx);
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return cache_req;
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}
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void
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CacheUnit::requestAgain(DynInstPtr inst, bool &service_request)
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{
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CacheReqPtr cache_req = dynamic_cast<CacheReqPtr>(findRequest(inst));
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assert(cache_req);
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// Check to see if this instruction is requesting the same command
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// or a different one
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if (cache_req->cmd != inst->curSkedEntry->cmd &&
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cache_req->instIdx == inst->curSkedEntry->idx) {
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// If different, then update command in the request
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cache_req->cmd = inst->curSkedEntry->cmd;
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DPRINTF(InOrderCachePort,
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"[tid:%i]: [sn:%i]: Updating the command for this "
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"instruction\n ", inst->readTid(), inst->seqNum);
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service_request = true;
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} else if (inst->curSkedEntry->idx != CacheUnit::InitSecondSplitRead &&
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inst->curSkedEntry->idx != CacheUnit::InitSecondSplitWrite) {
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// If same command, just check to see if memory access was completed
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// but dont try to re-execute
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DPRINTF(InOrderCachePort,
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"[tid:%i]: [sn:%i]: requesting this resource again\n",
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inst->readTid(), inst->seqNum);
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service_request = true;
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}
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}
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void
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CacheUnit::setupMemRequest(DynInstPtr inst, CacheReqPtr cache_req,
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int acc_size, int flags)
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{
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ThreadID tid = inst->readTid();
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Addr aligned_addr = inst->getMemAddr();
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if (!cache_req->is2ndSplit()) {
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if (cache_req->memReq == NULL) {
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cache_req->memReq =
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new Request(cpu->asid[tid], aligned_addr, acc_size, flags,
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inst->instAddr(), cpu->readCpuId(),
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tid);
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DPRINTF(InOrderCachePort, "[sn:%i] Created memReq @%x, ->%x\n",
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inst->seqNum, &cache_req->memReq, cache_req->memReq);
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}
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} else {
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assert(inst->splitInst);
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if (inst->splitMemReq == NULL) {
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inst->splitMemReq = new Request(cpu->asid[tid],
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inst->split2ndAddr,
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acc_size,
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flags,
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inst->instAddr(),
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cpu->readCpuId(),
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tid);
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}
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cache_req->memReq = inst->splitMemReq;
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}
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}
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void
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CacheUnit::doTLBAccess(DynInstPtr inst, CacheReqPtr cache_req, int acc_size,
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int flags, TheISA::TLB::Mode tlb_mode)
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{
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ThreadID tid = inst->readTid();
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//Addr aligned_addr = inst->getMemAddr();
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unsigned stage_num = cache_req->getStageNum();
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unsigned slot_idx = cache_req->getSlot();
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setupMemRequest(inst, cache_req, acc_size, flags);
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inst->fault =
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_tlb->translateAtomic(cache_req->memReq,
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cpu->thread[tid]->getTC(), tlb_mode);
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if (inst->fault != NoFault) {
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DPRINTF(InOrderTLB, "[tid:%i]: %s encountered while translating "
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"addr:%08p for [sn:%i].\n", tid, inst->fault->name(),
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cache_req->memReq->getVaddr(), inst->seqNum);
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cpu->pipelineStage[stage_num]->setResStall(cache_req, tid);
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tlbBlocked[tid] = true;
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cache_req->tlbStall = true;
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// schedule a time to process the tlb miss.
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// latency hardcoded to 1 (for now), but will be updated
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// when timing translation gets added in
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scheduleEvent(slot_idx, 1);
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} else {
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DPRINTF(InOrderTLB, "[tid:%i]: [sn:%i] virt. addr %08p translated "
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"to phys. addr:%08p.\n", tid, inst->seqNum,
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cache_req->memReq->getVaddr(),
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cache_req->memReq->getPaddr());
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}
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}
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|
|
Fault
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CacheUnit::read(DynInstPtr inst, Addr addr,
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uint8_t *data, unsigned size, unsigned flags)
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{
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CacheReqPtr cache_req = dynamic_cast<CacheReqPtr>(findRequest(inst));
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assert(cache_req && "Can't Find Instruction for Read!");
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|
|
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// The block size of our peer
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unsigned blockSize = this->cachePort->peerBlockSize();
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|
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//The size of the data we're trying to read.
|
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int fullSize = size;
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inst->totalSize = size;
|
|
|
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if (inst->traceData) {
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inst->traceData->setAddr(addr);
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|
}
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|
|
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if (inst->split2ndAccess) {
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size = inst->split2ndSize;
|
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cache_req->splitAccess = true;
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cache_req->split2ndAccess = true;
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DPRINTF(InOrderCachePort, "[sn:%i] Split Read Access (2 of 2) for "
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"(%#x, %#x).\n", inst->seqNum, inst->getMemAddr(),
|
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inst->split2ndAddr);
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}
|
|
|
|
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//The address of the second part of this access if it needs to be split
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//across a cache line boundary.
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Addr secondAddr = roundDown(addr + size - 1, blockSize);
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|
|
|
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if (secondAddr > addr && !inst->split2ndAccess) {
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|
|
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if (!inst->splitInst) {
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DPRINTF(InOrderCachePort, "%i: sn[%i] Split Read Access (1 of 2) for "
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"(%#x, %#x).\n", curTick(), inst->seqNum, addr, secondAddr);
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unsigned stage_num = cache_req->getStageNum();
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unsigned cmd = inst->curSkedEntry->cmd;
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// 1. Make A New Inst. Schedule w/Split Read/Complete Entered on
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// the schedule
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// ==============================
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// 2. Reassign curSkedPtr to current command (InitiateRead) on new
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// schedule
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|
// ==============================
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inst->splitInst = true;
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inst->setBackSked(cpu->createBackEndSked(inst));
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inst->curSkedEntry = inst->backSked->find(stage_num, cmd);
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} else {
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|
DPRINTF(InOrderCachePort, "[tid:%i] [sn:%i] Retrying Split Read "
|
|
"Access (1 of 2) for (%#x, %#x).\n", inst->readTid(),
|
|
inst->seqNum, addr, secondAddr);
|
|
}
|
|
|
|
// Save All "Total" Split Information
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|
// ==============================
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|
inst->splitMemData = new uint8_t[size];
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|
|
|
// Split Information for First Access
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|
// ==============================
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|
size = secondAddr - addr;
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|
cache_req->splitAccess = true;
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|
|
|
// Split Information for Second Access
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|
// ==============================
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|
inst->split2ndSize = addr + fullSize - secondAddr;
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|
inst->split2ndAddr = secondAddr;
|
|
inst->split2ndDataPtr = inst->splitMemData + size;
|
|
inst->split2ndFlags = flags;
|
|
}
|
|
|
|
doTLBAccess(inst, cache_req, size, flags, TheISA::TLB::Read);
|
|
|
|
if (inst->fault == NoFault) {
|
|
if (!cache_req->splitAccess) {
|
|
cache_req->reqData = new uint8_t[size];
|
|
doCacheAccess(inst, NULL);
|
|
} else {
|
|
if (!inst->split2ndAccess) {
|
|
cache_req->reqData = inst->splitMemData;
|
|
} else {
|
|
cache_req->reqData = inst->split2ndDataPtr;
|
|
}
|
|
|
|
doCacheAccess(inst, NULL, cache_req);
|
|
}
|
|
}
|
|
|
|
return inst->fault;
|
|
}
|
|
|
|
Fault
|
|
CacheUnit::write(DynInstPtr inst, uint8_t *data, unsigned size,
|
|
Addr addr, unsigned flags, uint64_t *write_res)
|
|
{
|
|
CacheReqPtr cache_req = dynamic_cast<CacheReqPtr>(findRequest(inst));
|
|
assert(cache_req && "Can't Find Instruction for Write!");
|
|
|
|
// The block size of our peer
|
|
unsigned blockSize = this->cachePort->peerBlockSize();
|
|
|
|
//The size of the data we're trying to write.
|
|
int fullSize = size;
|
|
inst->totalSize = size;
|
|
|
|
if (inst->traceData) {
|
|
inst->traceData->setAddr(addr);
|
|
}
|
|
|
|
if (inst->split2ndAccess) {
|
|
size = inst->split2ndSize;
|
|
cache_req->splitAccess = true;
|
|
cache_req->split2ndAccess = true;
|
|
|
|
DPRINTF(InOrderCachePort, "[sn:%i] Split Write Access (2 of 2) for "
|
|
"(%#x, %#x).\n", inst->seqNum, inst->getMemAddr(),
|
|
inst->split2ndAddr);
|
|
}
|
|
|
|
//The address of the second part of this access if it needs to be split
|
|
//across a cache line boundary.
|
|
Addr secondAddr = roundDown(addr + size - 1, blockSize);
|
|
|
|
if (secondAddr > addr && !inst->split2ndAccess) {
|
|
|
|
DPRINTF(InOrderCachePort, "[sn:%i] Split Write Access (1 of 2) for "
|
|
"(%#x, %#x).\n", inst->seqNum, addr, secondAddr);
|
|
|
|
// Save All "Total" Split Information
|
|
// ==============================
|
|
inst->splitInst = true;
|
|
|
|
if (!inst->splitInstSked) {
|
|
assert(0 && "Split Requests Not Supported for Now...");
|
|
|
|
// Schedule Split Read/Complete for Instruction
|
|
// ==============================
|
|
int stage_num = cache_req->getStageNum();
|
|
RSkedPtr inst_sked = (stage_num >= ThePipeline::BackEndStartStage) ?
|
|
inst->backSked : inst->frontSked;
|
|
|
|
// this is just an arbitrarily high priority to ensure that this
|
|
// gets pushed to the back of the list
|
|
int stage_pri = 20;
|
|
|
|
int isplit_cmd = CacheUnit::InitSecondSplitWrite;
|
|
inst_sked->push(new
|
|
ScheduleEntry(stage_num,
|
|
stage_pri,
|
|
cpu->resPool->getResIdx(DCache),
|
|
isplit_cmd,
|
|
1));
|
|
|
|
int csplit_cmd = CacheUnit::CompleteSecondSplitWrite;
|
|
inst_sked->push(new
|
|
ScheduleEntry(stage_num + 1,
|
|
1/*stage_pri*/,
|
|
cpu->resPool->getResIdx(DCache),
|
|
csplit_cmd,
|
|
1));
|
|
inst->splitInstSked = true;
|
|
} else {
|
|
DPRINTF(InOrderCachePort, "[tid:%i] sn:%i] Retrying Split Read "
|
|
"Access (1 of 2) for (%#x, %#x).\n",
|
|
inst->readTid(), inst->seqNum, addr, secondAddr);
|
|
}
|
|
|
|
|
|
|
|
// Split Information for First Access
|
|
// ==============================
|
|
size = secondAddr - addr;
|
|
cache_req->splitAccess = true;
|
|
|
|
// Split Information for Second Access
|
|
// ==============================
|
|
inst->split2ndSize = addr + fullSize - secondAddr;
|
|
inst->split2ndAddr = secondAddr;
|
|
inst->split2ndFlags = flags;
|
|
inst->splitInstSked = true;
|
|
}
|
|
|
|
doTLBAccess(inst, cache_req, size, flags, TheISA::TLB::Write);
|
|
|
|
if (inst->fault == NoFault) {
|
|
if (!cache_req->splitAccess) {
|
|
cache_req->reqData = new uint8_t[size];
|
|
memcpy(cache_req->reqData, data, size);
|
|
|
|
//inst->split2ndStoreDataPtr = cache_req->reqData;
|
|
//inst->split2ndStoreDataPtr += size;
|
|
|
|
doCacheAccess(inst, write_res);
|
|
} else {
|
|
doCacheAccess(inst, write_res, cache_req);
|
|
}
|
|
|
|
}
|
|
|
|
return inst->fault;
|
|
}
|
|
|
|
|
|
void
|
|
CacheUnit::execute(int slot_num)
|
|
{
|
|
CacheReqPtr cache_req = dynamic_cast<CacheReqPtr>(reqs[slot_num]);
|
|
assert(cache_req);
|
|
|
|
if (cachePortBlocked &&
|
|
(cache_req->cmd == InitiateReadData ||
|
|
cache_req->cmd == InitiateWriteData ||
|
|
cache_req->cmd == InitSecondSplitRead ||
|
|
cache_req->cmd == InitSecondSplitWrite)) {
|
|
DPRINTF(InOrderCachePort, "Cache Port Blocked. Cannot Access\n");
|
|
cache_req->done(false);
|
|
return;
|
|
}
|
|
|
|
DynInstPtr inst = cache_req->inst;
|
|
#if TRACING_ON
|
|
ThreadID tid = inst->readTid();
|
|
std::string acc_type = "write";
|
|
#endif
|
|
|
|
inst->fault = NoFault;
|
|
|
|
switch (cache_req->cmd)
|
|
{
|
|
|
|
case InitiateReadData:
|
|
#if TRACING_ON
|
|
acc_type = "read";
|
|
#endif
|
|
case InitiateWriteData:
|
|
if (cachePortBlocked) {
|
|
DPRINTF(InOrderCachePort, "Cache Port Blocked. Cannot Access\n");
|
|
cache_req->done(false);
|
|
return;
|
|
}
|
|
|
|
DPRINTF(InOrderCachePort,
|
|
"[tid:%u]: [sn:%i] Initiating data %s access to %s for "
|
|
"addr. %08p\n", tid, inst->seqNum, acc_type, name(),
|
|
cache_req->inst->getMemAddr());
|
|
|
|
inst->setCurResSlot(slot_num);
|
|
|
|
if (inst->isDataPrefetch() || inst->isInstPrefetch()) {
|
|
inst->execute();
|
|
} else {
|
|
inst->initiateAcc();
|
|
}
|
|
|
|
break;
|
|
|
|
case InitSecondSplitRead:
|
|
DPRINTF(InOrderCachePort,
|
|
"[tid:%u]: [sn:%i] Initiating split data read access to %s "
|
|
"for addr. %08p\n", tid, inst->seqNum, name(),
|
|
cache_req->inst->split2ndAddr);
|
|
inst->split2ndAccess = true;
|
|
assert(inst->split2ndAddr != 0);
|
|
read(inst, inst->split2ndAddr, &inst->split2ndData,
|
|
inst->totalSize, inst->split2ndFlags);
|
|
break;
|
|
|
|
case InitSecondSplitWrite:
|
|
DPRINTF(InOrderCachePort,
|
|
"[tid:%u]: [sn:%i] Initiating split data write access to %s "
|
|
"for addr. %08p\n", tid, inst->seqNum, name(),
|
|
cache_req->inst->getMemAddr());
|
|
|
|
inst->split2ndAccess = true;
|
|
assert(inst->split2ndAddr != 0);
|
|
write(inst, &inst->split2ndData, inst->totalSize,
|
|
inst->split2ndAddr, inst->split2ndFlags, NULL);
|
|
break;
|
|
|
|
case CompleteReadData:
|
|
DPRINTF(InOrderCachePort,
|
|
"[tid:%i]: [sn:%i]: Trying to Complete Data Read Access\n",
|
|
tid, inst->seqNum);
|
|
//@todo: timing translations need to check here...
|
|
assert(!inst->isInstPrefetch() && "Can't Handle Inst. Prefecthes");
|
|
if (cache_req->isMemAccComplete() || inst->isDataPrefetch()) {
|
|
finishCacheUnitReq(inst, cache_req);
|
|
} else {
|
|
DPRINTF(InOrderStall, "STALL: [tid:%i]: Data miss from %08p\n",
|
|
tid, cache_req->inst->getMemAddr());
|
|
cache_req->setCompleted(false);
|
|
cache_req->setMemStall(true);
|
|
}
|
|
break;
|
|
|
|
case CompleteWriteData:
|
|
DPRINTF(InOrderCachePort,
|
|
"[tid:%i]: [sn:%i]: Trying to Complete Data Write Access\n",
|
|
tid, inst->seqNum);
|
|
//@todo: check that timing translation is finished here
|
|
if (cache_req->dataPkt->isRead()) {
|
|
assert(cache_req->memReq->isCondSwap() ||
|
|
cache_req->memReq->isLLSC() ||
|
|
cache_req->memReq->isSwap());
|
|
|
|
if (!cache_req->isMemAccComplete()) {
|
|
DPRINTF(InOrderStall, "STALL: [tid:%i]: Data miss from %08p\n",
|
|
tid, cache_req->inst->getMemAddr());
|
|
cache_req->setCompleted(false);
|
|
cache_req->setMemStall(true);
|
|
return;
|
|
}
|
|
}
|
|
|
|
if (cache_req->isMemAccPending()) {
|
|
cache_req->dataPkt->reqData = cache_req->reqData;
|
|
cache_req->dataPkt->memReq = cache_req->memReq;
|
|
}
|
|
|
|
//@todo: if split inst save data
|
|
|
|
finishCacheUnitReq(inst, cache_req);
|
|
break;
|
|
|
|
case CompleteSecondSplitRead:
|
|
DPRINTF(InOrderCachePort,
|
|
"[tid:%i]: [sn:%i]: Trying to Complete Split Data Read "
|
|
"Access\n", tid, inst->seqNum);
|
|
|
|
//@todo: check that timing translation is finished here
|
|
assert(!inst->isInstPrefetch() && "Can't Handle Inst. Prefecthes");
|
|
if (cache_req->isMemAccComplete() || inst->isDataPrefetch()) {
|
|
finishCacheUnitReq(inst, cache_req);
|
|
} else {
|
|
DPRINTF(InOrderStall, "STALL: [tid:%i]: Data miss from %08p\n",
|
|
tid, cache_req->inst->split2ndAddr);
|
|
cache_req->setCompleted(false);
|
|
cache_req->setMemStall(true);
|
|
}
|
|
break;
|
|
|
|
case CompleteSecondSplitWrite:
|
|
DPRINTF(InOrderCachePort,
|
|
"[tid:%i]: [sn:%i]: Trying to Complete Split Data Write "
|
|
"Access\n", tid, inst->seqNum);
|
|
//@todo: illegal to have a unaligned cond.swap or llsc?
|
|
assert(!cache_req->memReq->isSwap() && !cache_req->memReq->isCondSwap() && !cache_req->memReq->isLLSC());
|
|
|
|
if (cache_req->isMemAccPending()) {
|
|
cache_req->dataPkt->reqData = cache_req->reqData;
|
|
cache_req->dataPkt->memReq = cache_req->memReq;
|
|
}
|
|
|
|
//@todo: check that timing translation is finished here
|
|
finishCacheUnitReq(inst, cache_req);
|
|
break;
|
|
|
|
default:
|
|
fatal("Unrecognized command to %s", resName);
|
|
}
|
|
}
|
|
|
|
void
|
|
CacheUnit::finishCacheUnitReq(DynInstPtr inst, CacheRequest *cache_req)
|
|
{
|
|
removeAddrDependency(inst);
|
|
cache_req->setMemStall(false);
|
|
cache_req->done();
|
|
}
|
|
|
|
void
|
|
CacheUnit::buildDataPacket(CacheRequest *cache_req)
|
|
{
|
|
// Check for LL/SC and if so change command
|
|
if (cache_req->memReq->isLLSC() && cache_req->pktCmd == MemCmd::ReadReq) {
|
|
cache_req->pktCmd = MemCmd::LoadLockedReq;
|
|
}
|
|
|
|
if (cache_req->pktCmd == MemCmd::WriteReq) {
|
|
cache_req->pktCmd =
|
|
cache_req->memReq->isSwap() ? MemCmd::SwapReq :
|
|
(cache_req->memReq->isLLSC() ? MemCmd::StoreCondReq
|
|
: MemCmd::WriteReq);
|
|
}
|
|
|
|
cache_req->dataPkt = new CacheReqPacket(cache_req,
|
|
cache_req->pktCmd,
|
|
Packet::Broadcast,
|
|
cache_req->instIdx);
|
|
DPRINTF(InOrderCachePort, "[slot:%i]: Slot marked for %x [pkt:%x->%x]\n",
|
|
cache_req->getSlot(),
|
|
cache_req->dataPkt->getAddr(),
|
|
&cache_req->dataPkt,
|
|
cache_req->dataPkt);
|
|
|
|
cache_req->dataPkt->hasSlot = true;
|
|
cache_req->dataPkt->dataStatic(cache_req->reqData);
|
|
}
|
|
|
|
void
|
|
CacheUnit::doCacheAccess(DynInstPtr inst, uint64_t *write_res,
|
|
CacheReqPtr split_req)
|
|
{
|
|
Fault fault = NoFault;
|
|
#if TRACING_ON
|
|
ThreadID tid = inst->readTid();
|
|
#endif
|
|
bool do_access = true; // flag to suppress cache access
|
|
|
|
// Special Handling if this is a split request
|
|
CacheReqPtr cache_req;
|
|
if (split_req == NULL)
|
|
cache_req = dynamic_cast<CacheReqPtr>(reqs[inst->getCurResSlot()]);
|
|
else {
|
|
cache_req = split_req;
|
|
assert(0);
|
|
}
|
|
|
|
// Make a new packet inside the CacheRequest object
|
|
assert(cache_req);
|
|
buildDataPacket(cache_req);
|
|
|
|
// Special Handling for LL/SC or Compare/Swap
|
|
bool is_write = cache_req->dataPkt->isWrite();
|
|
RequestPtr mem_req = cache_req->dataPkt->req;
|
|
if (is_write) {
|
|
DPRINTF(InOrderCachePort,
|
|
"[tid:%u]: [sn:%i]: Storing data: %s\n",
|
|
tid, inst->seqNum,
|
|
printMemData(cache_req->dataPkt->getPtr<uint8_t>(),
|
|
cache_req->dataPkt->getSize()));
|
|
|
|
if (mem_req->isCondSwap()) {
|
|
assert(write_res);
|
|
cache_req->memReq->setExtraData(*write_res);
|
|
}
|
|
if (mem_req->isLLSC()) {
|
|
assert(cache_req->inst->isStoreConditional());
|
|
DPRINTF(InOrderCachePort, "Evaluating Store Conditional access\n");
|
|
do_access = TheISA::handleLockedWrite(cpu, mem_req);
|
|
}
|
|
}
|
|
|
|
// Finally, go ahead and make the access if we can...
|
|
DPRINTF(InOrderCachePort,
|
|
"[tid:%i] [sn:%i] attempting to access cache for addr %08p\n",
|
|
tid, inst->seqNum, cache_req->dataPkt->getAddr());
|
|
|
|
if (do_access) {
|
|
if (!cachePort->sendTiming(cache_req->dataPkt)) {
|
|
DPRINTF(InOrderCachePort,
|
|
"[tid:%i] [sn:%i] cannot access cache, because port "
|
|
"is blocked. now waiting to retry request\n", tid,
|
|
inst->seqNum);
|
|
delete cache_req->dataPkt;
|
|
cache_req->dataPkt = NULL;
|
|
|
|
delete cache_req->memReq;
|
|
cache_req->memReq = NULL;
|
|
|
|
cache_req->done(false);
|
|
cachePortBlocked = true;
|
|
} else {
|
|
DPRINTF(InOrderCachePort,
|
|
"[tid:%i] [sn:%i] is now waiting for cache response\n",
|
|
tid, inst->seqNum);
|
|
cache_req->setCompleted();
|
|
cache_req->setMemAccPending();
|
|
cachePortBlocked = false;
|
|
}
|
|
} else if (mem_req->isLLSC()){
|
|
// Store-Conditional instructions complete even if they "failed"
|
|
assert(cache_req->inst->isStoreConditional());
|
|
cache_req->setCompleted(true);
|
|
|
|
DPRINTF(LLSC,
|
|
"[tid:%i]: T%i Ignoring Failed Store Conditional Access\n",
|
|
tid, tid);
|
|
|
|
processCacheCompletion(cache_req->dataPkt);
|
|
} else {
|
|
delete cache_req->dataPkt;
|
|
cache_req->dataPkt = NULL;
|
|
|
|
delete cache_req->memReq;
|
|
cache_req->memReq = NULL;
|
|
|
|
// Make cache request again since access due to
|
|
// inability to access
|
|
DPRINTF(InOrderStall, "STALL: \n");
|
|
cache_req->done(false);
|
|
}
|
|
|
|
}
|
|
|
|
bool
|
|
CacheUnit::processSquash(CacheReqPacket *cache_pkt)
|
|
{
|
|
// The resource may no longer be actively servicing this
|
|
// packet. Scenarios like a store that has been sent to the
|
|
// memory system or access that's been squashed. If that's
|
|
// the case, we can't access the request slot because it
|
|
// will be either invalid or servicing another request.
|
|
if (!cache_pkt->hasSlot) {
|
|
DPRINTF(InOrderCachePort,
|
|
"%x does not have a slot in unit, ignoring.\n",
|
|
cache_pkt->getAddr());
|
|
|
|
if (cache_pkt->reqData) {
|
|
delete [] cache_pkt->reqData;
|
|
cache_pkt->reqData = NULL;
|
|
}
|
|
|
|
if (cache_pkt->memReq) {
|
|
delete cache_pkt->memReq;
|
|
cache_pkt->memReq = NULL;
|
|
}
|
|
|
|
delete cache_pkt;
|
|
cache_pkt = NULL;
|
|
cpu->wakeCPU();
|
|
return true;
|
|
} else {
|
|
DPRINTF(InOrderCachePort, "%x has slot %i\n",
|
|
cache_pkt->getAddr(), cache_pkt->cacheReq->getSlot());
|
|
}
|
|
|
|
|
|
// It's possible that the request is squashed but the
|
|
// packet is still acknowledged by the resource. Squashes
|
|
// should happen at the end of the cycles and trigger the
|
|
// code above, but if not, this would handle any timing
|
|
// variations due to diff. user parameters.
|
|
if (cache_pkt->cacheReq->isSquashed()) {
|
|
DPRINTF(InOrderCachePort,
|
|
"Ignoring completion of squashed access, [tid:%i] [sn:%i]\n",
|
|
cache_pkt->cacheReq->getInst()->readTid(),
|
|
cache_pkt->cacheReq->getInst()->seqNum);
|
|
|
|
cache_pkt->cacheReq->setMemAccPending(false);
|
|
cache_pkt->cacheReq->freeSlot();
|
|
delete cache_pkt;
|
|
cache_pkt = NULL;
|
|
cpu->wakeCPU();
|
|
return true;
|
|
}
|
|
|
|
|
|
return false;
|
|
}
|
|
|
|
void
|
|
CacheUnit::processCacheCompletion(PacketPtr pkt)
|
|
{
|
|
CacheReqPacket* cache_pkt = dynamic_cast<CacheReqPacket*>(pkt);
|
|
assert(cache_pkt);
|
|
|
|
DPRINTF(InOrderCachePort, "Finished request for %x [pkt:%x->%x]\n",
|
|
pkt->getAddr(), &cache_pkt, cache_pkt);
|
|
|
|
//@todo: process Squashed Completion
|
|
if (processSquash(cache_pkt))
|
|
return;
|
|
|
|
CacheRequest *cache_req = dynamic_cast<CacheReqPtr>(
|
|
findRequest(cache_pkt->cacheReq->getInst(), cache_pkt->instIdx));
|
|
|
|
if (!cache_req) {
|
|
panic("[tid:%u]: [sn:%i]: Can't find slot for cache access to "
|
|
"addr. %08p\n", cache_pkt->cacheReq->getInst()->readTid(),
|
|
cache_pkt->cacheReq->getInst()->seqNum,
|
|
cache_pkt->cacheReq->getInst()->getMemAddr());
|
|
}
|
|
|
|
assert(cache_req);
|
|
assert(cache_req == cache_pkt->cacheReq);
|
|
|
|
DPRINTF(InOrderCachePort,
|
|
"[tid:%u]: [sn:%i]: [slot:%i] Waking from cache access (vaddr.%08p, paddr:%08p)\n",
|
|
cache_pkt->cacheReq->getInst()->readTid(),
|
|
cache_pkt->cacheReq->getInst()->seqNum,
|
|
cache_req->getSlot(),
|
|
cache_pkt->req->getVaddr(),
|
|
cache_pkt->req->getPaddr());
|
|
|
|
// Get resource request info
|
|
unsigned stage_num = cache_req->getStageNum();
|
|
DynInstPtr inst = cache_req->inst;
|
|
ThreadID tid = cache_req->inst->readTid();
|
|
|
|
assert(!cache_req->isSquashed());
|
|
assert(inst->staticInst && inst->isMemRef());
|
|
|
|
|
|
DPRINTF(InOrderCachePort,
|
|
"[tid:%u]: [sn:%i]: Processing cache access\n",
|
|
tid, inst->seqNum);
|
|
|
|
PacketPtr split_pkt = NULL;
|
|
if (inst->splitInst) {
|
|
inst->splitFinishCnt++;
|
|
|
|
if (inst->splitFinishCnt == 2) {
|
|
cache_req->memReq->setVirt(0/*inst->tid*/,
|
|
inst->getMemAddr(),
|
|
inst->totalSize,
|
|
0,
|
|
0);
|
|
|
|
split_pkt = new Packet(cache_req->memReq, cache_req->pktCmd,
|
|
Packet::Broadcast);
|
|
split_pkt->dataStatic(inst->splitMemData);
|
|
|
|
DPRINTF(InOrderCachePort, "Completing Split Access.\n");
|
|
inst->completeAcc(split_pkt);
|
|
}
|
|
} else {
|
|
inst->completeAcc(cache_pkt);
|
|
}
|
|
|
|
inst->setExecuted();
|
|
|
|
if (inst->isLoad()) {
|
|
assert(cache_pkt->isRead());
|
|
|
|
if (cache_pkt->req->isLLSC()) {
|
|
DPRINTF(InOrderCachePort,
|
|
"[tid:%u]: Handling Load-Linked for [sn:%u]\n",
|
|
tid, inst->seqNum);
|
|
TheISA::handleLockedRead(cpu, cache_pkt->req);
|
|
}
|
|
|
|
DPRINTF(InOrderCachePort,
|
|
"[tid:%u]: [sn:%i]: Bytes loaded were: %s\n",
|
|
tid, inst->seqNum,
|
|
(split_pkt) ? printMemData(split_pkt->getPtr<uint8_t>(),
|
|
split_pkt->getSize()) :
|
|
printMemData(cache_pkt->getPtr<uint8_t>(),
|
|
cache_pkt->getSize()));
|
|
} else if(inst->isStore()) {
|
|
assert(cache_pkt->isWrite());
|
|
|
|
DPRINTF(InOrderCachePort,
|
|
"[tid:%u]: [sn:%i]: Bytes stored were: %s\n",
|
|
tid, inst->seqNum,
|
|
(split_pkt) ? printMemData(split_pkt->getPtr<uint8_t>(),
|
|
split_pkt->getSize()) :
|
|
printMemData(cache_pkt->getPtr<uint8_t>(),
|
|
cache_pkt->getSize()));
|
|
}
|
|
|
|
DPRINTF(InOrderCachePort, "Deleting packets %x (%x).\n",
|
|
cache_pkt, cache_req->dataPkt);
|
|
|
|
if (split_pkt) {
|
|
delete split_pkt;
|
|
split_pkt = NULL;
|
|
}
|
|
|
|
cache_req->setMemAccPending(false);
|
|
cache_req->setMemAccCompleted();
|
|
|
|
if (cache_req->isMemStall() &&
|
|
cpu->threadModel == InOrderCPU::SwitchOnCacheMiss) {
|
|
DPRINTF(InOrderCachePort, "[tid:%u] Waking up from Cache Miss.\n",
|
|
tid);
|
|
|
|
cpu->activateContext(tid);
|
|
|
|
DPRINTF(ThreadModel, "Activating [tid:%i] after return from cache"
|
|
"miss.\n", tid);
|
|
}
|
|
|
|
// Wake up the CPU (if it went to sleep and was waiting on this
|
|
// completion event).
|
|
cpu->wakeCPU();
|
|
|
|
DPRINTF(Activity, "[tid:%u] Activating %s due to cache completion\n",
|
|
tid, cpu->pipelineStage[stage_num]->name());
|
|
|
|
cpu->switchToActive(stage_num);
|
|
}
|
|
|
|
void
|
|
CacheUnit::recvRetry()
|
|
{
|
|
DPRINTF(InOrderCachePort, "Unblocking Cache Port. \n");
|
|
|
|
assert(cachePortBlocked);
|
|
|
|
// Clear the cache port for use again
|
|
cachePortBlocked = false;
|
|
|
|
cpu->wakeCPU();
|
|
}
|
|
|
|
CacheUnitEvent::CacheUnitEvent()
|
|
: ResourceEvent()
|
|
{ }
|
|
|
|
void
|
|
CacheUnitEvent::process()
|
|
{
|
|
DynInstPtr inst = resource->reqs[slotIdx]->inst;
|
|
int stage_num = resource->reqs[slotIdx]->getStageNum();
|
|
ThreadID tid = inst->threadNumber;
|
|
CacheReqPtr req_ptr = dynamic_cast<CacheReqPtr>(resource->reqs[slotIdx]);
|
|
|
|
DPRINTF(InOrderTLB, "Waking up from TLB Miss caused by [sn:%i].\n",
|
|
inst->seqNum);
|
|
|
|
CacheUnit* tlb_res = dynamic_cast<CacheUnit*>(resource);
|
|
assert(tlb_res);
|
|
|
|
//@todo: eventually, we should do a timing translation w/
|
|
// hw page table walk on tlb miss
|
|
DPRINTF(Fault, "Handling Fault %s : [sn:%i] %x\n", inst->fault->name(), inst->seqNum, inst->getMemAddr());
|
|
inst->fault->invoke(tlb_res->cpu->tcBase(tid), inst->staticInst);
|
|
|
|
tlb_res->tlbBlocked[tid] = false;
|
|
|
|
tlb_res->cpu->pipelineStage[stage_num]->
|
|
unsetResStall(tlb_res->reqs[slotIdx], tid);
|
|
|
|
req_ptr->tlbStall = false;
|
|
|
|
//@todo: timing translation needs to have some type of independent
|
|
// info regarding if it's squashed or not so we can
|
|
// free up the resource if a request gets squashed in the middle
|
|
// of a table walk
|
|
if (req_ptr->isSquashed()) {
|
|
req_ptr->freeSlot();
|
|
}
|
|
|
|
tlb_res->cpu->wakeCPU();
|
|
}
|
|
|
|
void
|
|
CacheUnit::squashDueToMemStall(DynInstPtr inst, int stage_num,
|
|
InstSeqNum squash_seq_num, ThreadID tid)
|
|
{
|
|
// If squashing due to memory stall, then we do NOT want to
|
|
// squash the instruction that caused the stall so we
|
|
// increment the sequence number here to prevent that.
|
|
//
|
|
// NOTE: This is only for the SwitchOnCacheMiss Model
|
|
// NOTE: If you have multiple outstanding misses from the same
|
|
// thread then you need to reevaluate this code
|
|
// NOTE: squash should originate from
|
|
// pipeline_stage.cc:processInstSchedule
|
|
DPRINTF(InOrderCachePort, "Squashing above [sn:%u]\n",
|
|
squash_seq_num + 1);
|
|
|
|
squash(inst, stage_num, squash_seq_num + 1, tid);
|
|
}
|
|
|
|
void
|
|
CacheUnit::squashCacheRequest(CacheReqPtr req_ptr)
|
|
{
|
|
DynInstPtr inst = req_ptr->getInst();
|
|
|
|
req_ptr->setSquashed();
|
|
inst->setSquashed();
|
|
if (inst->validMemAddr()) {
|
|
DPRINTF(AddrDep, "Squash of [tid:%i] [sn:%i], attempting to "
|
|
"remove addr. %08p dependencies.\n",
|
|
inst->readTid(),
|
|
inst->seqNum,
|
|
inst->getMemAddr());
|
|
|
|
removeAddrDependency(inst);
|
|
}
|
|
}
|
|
|
|
|
|
void
|
|
CacheUnit::squash(DynInstPtr inst, int stage_num,
|
|
InstSeqNum squash_seq_num, ThreadID tid)
|
|
{
|
|
for (int i = 0; i < width; i++) {
|
|
ResReqPtr req_ptr = reqs[i];
|
|
|
|
if (req_ptr->valid &&
|
|
req_ptr->getInst()->readTid() == tid &&
|
|
req_ptr->getInst()->seqNum > squash_seq_num) {
|
|
|
|
DPRINTF(InOrderCachePort,
|
|
"[tid:%i] Squashing request from [sn:%i]\n",
|
|
req_ptr->getInst()->readTid(), req_ptr->getInst()->seqNum);
|
|
|
|
if (req_ptr->isSquashed()) {
|
|
DPRINTF(AddrDep, "Request for [tid:%i] [sn:%i] already "
|
|
"squashed, ignoring squash process.\n",
|
|
req_ptr->getInst()->readTid(),
|
|
req_ptr->getInst()->seqNum);
|
|
continue;
|
|
}
|
|
|
|
CacheReqPtr cache_req = dynamic_cast<CacheReqPtr>(req_ptr);
|
|
assert(cache_req);
|
|
|
|
squashCacheRequest(cache_req);
|
|
|
|
int req_slot_num = req_ptr->getSlot();
|
|
|
|
if (cache_req->tlbStall) {
|
|
tlbBlocked[tid] = false;
|
|
|
|
int stall_stage = reqs[req_slot_num]->getStageNum();
|
|
|
|
cpu->pipelineStage[stall_stage]->
|
|
unsetResStall(reqs[req_slot_num], tid);
|
|
}
|
|
|
|
if (cache_req->isMemAccPending()) {
|
|
cache_req->dataPkt->reqData = cache_req->reqData;
|
|
cache_req->dataPkt->memReq = cache_req->memReq;
|
|
}
|
|
|
|
if (!cache_req->tlbStall)
|
|
freeSlot(req_slot_num);
|
|
}
|
|
}
|
|
|
|
}
|
|
|
|
void
|
|
CacheRequest::clearRequest()
|
|
{
|
|
if (!memAccPending) {
|
|
if (reqData && !splitAccess)
|
|
delete [] reqData;
|
|
|
|
if (memReq) {
|
|
DPRINTF(InOrderCachePort, "Clearing request for %x...%x\n",
|
|
memReq->getVaddr(), (memReq->hasPaddr()) ? memReq->getPaddr() : 0);
|
|
delete memReq;
|
|
}
|
|
|
|
if (dataPkt)
|
|
delete dataPkt;
|
|
} else {
|
|
if (dataPkt) {
|
|
dataPkt->hasSlot = false;
|
|
DPRINTF(InOrderCachePort, "[slot:%i]: Slot unmarked for %x for [pkt:%x->%x]\n",
|
|
getSlot(), dataPkt->getAddr(), &dataPkt, dataPkt);
|
|
}
|
|
}
|
|
|
|
memReq = NULL;
|
|
reqData = NULL;
|
|
dataPkt = NULL;
|
|
memAccComplete = false;
|
|
memAccPending = false;
|
|
tlbStall = false;
|
|
splitAccess = false;
|
|
splitAccessNum = -1;
|
|
split2ndAccess = false;
|
|
instIdx = 0;
|
|
fetchBufferFill = false;
|
|
|
|
ResourceRequest::clearRequest();
|
|
}
|