These currently only hold the number of registers in a particular class, but can be extended in the future to hold other information about each class. The ISA class holds a vector of descriptors which other parts of gem5 can retrieve to set up storage for each class, etc. Currently, the RegClass enum is used to explicitly index into the vector of descriptors to get information about a particular class. Once enough information is stored in the descriptors, the other parts of gem5 should be able to set up for each register class generically, and the ISAs will be able to leave out or create new register classes without having to set up global plumbing for it. The more immediate benefit is that this should (mostly) parameterize away the ISA register constants to break another TheISA style dependency. Currently a global set of descriptors are set up in the BaseISA class using the old TheISA constants, but it should be easy to break those out and make the ISAs set up their own descriptors. That will bring arch/registers.hh significantly closer to being eliminated. Change-Id: I6d6d1256288f880391246b71045482a4a03c4198 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41733 Reviewed-by: Gabe Black <gabe.black@gmail.com> Maintainer: Gabe Black <gabe.black@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
231 lines
9.5 KiB
C++
231 lines
9.5 KiB
C++
/*
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* Copyright (c) 2016-2018 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* Copyright (c) 2013 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "cpu/o3/regfile.hh"
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#include "cpu/o3/free_list.hh"
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#include "arch/generic/types.hh"
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#include "cpu/o3/free_list.hh"
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PhysRegFile::PhysRegFile(unsigned _numPhysicalIntRegs,
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unsigned _numPhysicalFloatRegs,
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unsigned _numPhysicalVecRegs,
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unsigned _numPhysicalVecPredRegs,
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unsigned _numPhysicalCCRegs,
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unsigned _numPhysicalMiscRegs,
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VecMode vmode)
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: intRegFile(_numPhysicalIntRegs),
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floatRegFile(_numPhysicalFloatRegs),
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vectorRegFile(_numPhysicalVecRegs),
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vecPredRegFile(_numPhysicalVecPredRegs),
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ccRegFile(_numPhysicalCCRegs),
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numPhysicalIntRegs(_numPhysicalIntRegs),
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numPhysicalFloatRegs(_numPhysicalFloatRegs),
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numPhysicalVecRegs(_numPhysicalVecRegs),
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numPhysicalVecElemRegs(_numPhysicalVecRegs *
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TheISA::NumVecElemPerVecReg),
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numPhysicalVecPredRegs(_numPhysicalVecPredRegs),
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numPhysicalCCRegs(_numPhysicalCCRegs),
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totalNumRegs(_numPhysicalIntRegs
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+ _numPhysicalFloatRegs
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+ _numPhysicalVecRegs
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+ _numPhysicalVecRegs * TheISA::NumVecElemPerVecReg
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+ _numPhysicalVecPredRegs
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+ _numPhysicalCCRegs),
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vecMode(vmode)
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{
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PhysRegIndex phys_reg;
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PhysRegIndex flat_reg_idx = 0;
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// The initial batch of registers are the integer ones
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for (phys_reg = 0; phys_reg < numPhysicalIntRegs; phys_reg++) {
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intRegIds.emplace_back(IntRegClass, phys_reg, flat_reg_idx++);
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}
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// The next batch of the registers are the floating-point physical
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// registers; put them onto the floating-point free list.
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for (phys_reg = 0; phys_reg < numPhysicalFloatRegs; phys_reg++) {
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floatRegIds.emplace_back(FloatRegClass, phys_reg, flat_reg_idx++);
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}
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// The next batch of the registers are the vector physical
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// registers; put them onto the vector free list.
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for (phys_reg = 0; phys_reg < numPhysicalVecRegs; phys_reg++) {
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vectorRegFile[phys_reg].zero();
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vecRegIds.emplace_back(VecRegClass, phys_reg, flat_reg_idx++);
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}
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// The next batch of the registers are the vector element physical
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// registers; they refer to the same containers as the vector
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// registers, just a different (and incompatible) way to access
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// them; put them onto the vector free list.
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for (phys_reg = 0; phys_reg < numPhysicalVecRegs; phys_reg++) {
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for (ElemIndex eIdx = 0; eIdx < TheISA::NumVecElemPerVecReg; eIdx++) {
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vecElemIds.emplace_back(VecElemClass, phys_reg,
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eIdx, flat_reg_idx++);
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}
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}
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// The next batch of the registers are the predicate physical
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// registers; put them onto the predicate free list.
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for (phys_reg = 0; phys_reg < numPhysicalVecPredRegs; phys_reg++) {
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vecPredRegIds.emplace_back(VecPredRegClass, phys_reg, flat_reg_idx++);
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}
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// The rest of the registers are the condition-code physical
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// registers; put them onto the condition-code free list.
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for (phys_reg = 0; phys_reg < numPhysicalCCRegs; phys_reg++) {
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ccRegIds.emplace_back(CCRegClass, phys_reg, flat_reg_idx++);
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}
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// Misc regs have a fixed mapping but still need PhysRegIds.
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for (phys_reg = 0; phys_reg < _numPhysicalMiscRegs; phys_reg++) {
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miscRegIds.emplace_back(MiscRegClass, phys_reg, 0);
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}
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}
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void
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PhysRegFile::initFreeList(UnifiedFreeList *freeList)
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{
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// Initialize the free lists.
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int reg_idx = 0;
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// The initial batch of registers are the integer ones
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for (reg_idx = 0; reg_idx < numPhysicalIntRegs; reg_idx++) {
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assert(intRegIds[reg_idx].index() == reg_idx);
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}
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freeList->addRegs(intRegIds.begin(), intRegIds.end());
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// The next batch of the registers are the floating-point physical
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// registers; put them onto the floating-point free list.
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for (reg_idx = 0; reg_idx < numPhysicalFloatRegs; reg_idx++) {
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assert(floatRegIds[reg_idx].index() == reg_idx);
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}
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freeList->addRegs(floatRegIds.begin(), floatRegIds.end());
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/* The next batch of the registers are the vector physical
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* registers; put them onto the vector free list. */
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for (reg_idx = 0; reg_idx < numPhysicalVecRegs; reg_idx++) {
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assert(vecRegIds[reg_idx].index() == reg_idx);
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for (ElemIndex elemIdx = 0; elemIdx < TheISA::NumVecElemPerVecReg;
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elemIdx++) {
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assert(vecElemIds[reg_idx * TheISA::NumVecElemPerVecReg +
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elemIdx].index() == reg_idx);
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assert(vecElemIds[reg_idx * TheISA::NumVecElemPerVecReg +
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elemIdx].elemIndex() == elemIdx);
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}
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}
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/* depending on the mode we add the vector registers as whole units or
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* as different elements. */
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if (vecMode == Enums::Full)
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freeList->addRegs(vecRegIds.begin(), vecRegIds.end());
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else
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freeList->addRegs(vecElemIds.begin(), vecElemIds.end());
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// The next batch of the registers are the predicate physical
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// registers; put them onto the predicate free list.
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for (reg_idx = 0; reg_idx < numPhysicalVecPredRegs; reg_idx++) {
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assert(vecPredRegIds[reg_idx].index() == reg_idx);
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}
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freeList->addRegs(vecPredRegIds.begin(), vecPredRegIds.end());
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// The rest of the registers are the condition-code physical
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// registers; put them onto the condition-code free list.
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for (reg_idx = 0; reg_idx < numPhysicalCCRegs; reg_idx++) {
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assert(ccRegIds[reg_idx].index() == reg_idx);
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}
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freeList->addRegs(ccRegIds.begin(), ccRegIds.end());
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}
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PhysRegFile::IdRange
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PhysRegFile::getRegElemIds(PhysRegIdPtr reg)
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{
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panic_if(!reg->isVectorPhysReg(),
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"Trying to get elems of a %s register", reg->className());
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auto idx = reg->index();
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return std::make_pair(
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vecElemIds.begin() + idx * TheISA::NumVecElemPerVecReg,
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vecElemIds.begin() + (idx+1) * TheISA::NumVecElemPerVecReg);
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}
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PhysRegFile::IdRange
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PhysRegFile::getRegIds(RegClass cls)
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{
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switch (cls)
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{
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case IntRegClass:
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return std::make_pair(intRegIds.begin(), intRegIds.end());
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case FloatRegClass:
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return std::make_pair(floatRegIds.begin(), floatRegIds.end());
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case VecRegClass:
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return std::make_pair(vecRegIds.begin(), vecRegIds.end());
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case VecElemClass:
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return std::make_pair(vecElemIds.begin(), vecElemIds.end());
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case VecPredRegClass:
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return std::make_pair(vecPredRegIds.begin(), vecPredRegIds.end());
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case CCRegClass:
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return std::make_pair(ccRegIds.begin(), ccRegIds.end());
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case MiscRegClass:
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return std::make_pair(miscRegIds.begin(), miscRegIds.end());
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}
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/* There is no way to make an empty iterator */
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return std::make_pair(PhysIds::iterator(),
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PhysIds::iterator());
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}
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PhysRegIdPtr
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PhysRegFile::getTrueId(PhysRegIdPtr reg)
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{
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switch (reg->classValue()) {
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case VecRegClass:
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return &vecRegIds[reg->index()];
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case VecElemClass:
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return &vecElemIds[reg->index() * TheISA::NumVecElemPerVecReg +
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reg->elemIndex()];
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default:
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panic_if(!reg->isVectorPhysElem(),
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"Trying to get the register of a %s register", reg->className());
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}
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return nullptr;
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}
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