Giacomo Travaglini e79c4c6f03 arch-arm: RBIT instruction using mirroring func ...

The high speed bit-reversing function is now used
for the Aarch64/32 RBIT instruction implementation.

Change-Id: Id5a8a93d928d00fd33ec4061fbb586b8420a1c1b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5262
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

2017-10-20 15:33:40 +00:00

..

arch

arch-arm: RBIT instruction using mirroring func

2017-10-20 15:33:40 +00:00

base

base: Function for mirroring bits in variable length word

2017-10-20 15:33:40 +00:00

cpu

cpu-o3: Add M5_VAR_USED to variable

2017-10-19 23:03:58 +00:00

dev

dev: Make the IDE controller handle NULL simobject pointers.

2017-09-26 23:47:24 +00:00

doc

sim: Adding support for power models

2016-06-06 17:16:44 +01:00

doxygen

MEM: Put memory system document into doxygen

2012-09-25 11:49:41 -05:00

gpu-compute

gpu-compute: Refactor some Event subclasses to lambdas

2017-07-12 20:07:05 +00:00

kern

stats: Move the swpipl function into the Alpha kernel stats.

2017-09-11 04:59:01 +00:00

mem

mem: Signal the local monitor when clearing the global monitor

2017-10-13 08:41:08 +00:00

proto

mem: Add a "map" of packet IDs to strings in probe traces.

2017-09-25 21:13:49 +00:00

python

util: Make dot_writer ignore NULL simobjects.

2017-09-26 23:47:39 +00:00

sim

sim-se: Fix mremap for downward growing mmap regions

2017-09-28 07:55:18 +00:00

unittest

python: Use PyBind11 instead of SWIG for Python wrappers

2017-05-02 12:37:32 +00:00

Doxyfile

Doxygen: Update the version of the Doxyfile

2012-10-11 06:38:42 -04:00

SConscript

scons: Fix the regression tests.

2017-10-19 00:41:14 +00:00