bcf455755e
Update the PLIC based on the [riscv-plic-spec](https://github.com/riscv/riscv-plic-spec) in the PR: - Support customized PLIC hardID and privilege mode configuration - Backward compatable with the n_contexts parameter, will generate the config like {0,M}, {0,S}, {1,M} ... Change-Id: Ibff736827edb7c97921e01fa27f503574a27a562
542 lines
20 KiB
Python
542 lines
20 KiB
Python
# Copyright (c) 2021 The Regents of the University of California
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# Copyright (c) 2022 EXAscale Performance SYStems (EXAPSYS)
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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import os
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from typing import List
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import m5
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from m5.objects import (
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AddrRange,
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BadAddr,
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Bridge,
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CowDiskImage,
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Frequency,
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GenericRiscvPciHost,
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HiFive,
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IGbE_e1000,
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IOXBar,
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PMAChecker,
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Port,
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RawDiskImage,
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RiscvBootloaderKernelWorkload,
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RiscvMmioVirtIO,
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RiscvRTC,
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VirtIOBlock,
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VirtIORng,
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)
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from m5.util.fdthelper import (
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Fdt,
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FdtNode,
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FdtProperty,
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FdtPropertyStrings,
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FdtPropertyWords,
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FdtState,
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)
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from ...isas import ISA
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from ...resources.resource import AbstractResource
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from ...utils.override import overrides
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from ..cachehierarchies.abstract_cache_hierarchy import AbstractCacheHierarchy
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from ..memory.abstract_memory_system import AbstractMemorySystem
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from ..processors.abstract_processor import AbstractProcessor
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from .abstract_system_board import AbstractSystemBoard
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from .kernel_disk_workload import KernelDiskWorkload
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class RiscvBoard(AbstractSystemBoard, KernelDiskWorkload):
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"""
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A board capable of full system simulation for RISC-V.
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At a high-level, this is based on the HiFive Unmatched board from SiFive.
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This board assumes that you will be booting Linux.
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**Limitations**
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* Only works with classic caches
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"""
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def __init__(
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self,
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clk_freq: str,
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processor: AbstractProcessor,
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memory: AbstractMemorySystem,
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cache_hierarchy: AbstractCacheHierarchy,
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) -> None:
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super().__init__(clk_freq, processor, memory, cache_hierarchy)
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if processor.get_isa() != ISA.RISCV:
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raise Exception(
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"The RISCVBoard requires a processor using the"
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"RISCV ISA. Current processor ISA: "
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f"'{processor.get_isa().name}'."
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)
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@overrides(AbstractSystemBoard)
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def _setup_board(self) -> None:
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self.workload = RiscvBootloaderKernelWorkload()
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# Contains a CLINT, PLIC, UART, and some functions for the dtb, etc.
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self.platform = HiFive()
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# Note: This only works with single threaded cores.
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self.platform.plic.hart_config = ",".join(
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["MS" for _ in range(self.processor.get_num_cores())]
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)
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self.platform.attachPlic()
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self.platform.clint.num_threads = self.processor.get_num_cores()
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# Add the RTC
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# TODO: Why 100MHz? Does something else need to change when this does?
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self.platform.rtc = RiscvRTC(frequency=Frequency("100MHz"))
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self.platform.clint.int_pin = self.platform.rtc.int_pin
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# Incoherent I/O bus
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self.iobus = IOXBar()
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self.iobus.badaddr_responder = BadAddr()
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self.iobus.default = self.iobus.badaddr_responder.pio
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# The virtio disk
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self.disk = RiscvMmioVirtIO(
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vio=VirtIOBlock(),
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interrupt_id=0x8,
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pio_size=4096,
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pio_addr=0x10008000,
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)
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# The virtio rng
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self.rng = RiscvMmioVirtIO(
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vio=VirtIORng(),
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interrupt_id=0x8,
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pio_size=4096,
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pio_addr=0x10007000,
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)
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# Note: This overrides the platform's code because the platform isn't
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# general enough.
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self._on_chip_devices = [self.platform.clint, self.platform.plic]
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self._off_chip_devices = [self.platform.uart, self.disk, self.rng]
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def _setup_io_devices(self) -> None:
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"""Connect the I/O devices to the I/O bus."""
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# Add PCI
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self.platform.pci_host.pio = self.iobus.mem_side_ports
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# Add Ethernet card
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self.ethernet = IGbE_e1000(
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pci_bus=0, pci_dev=0, pci_func=0, InterruptLine=1, InterruptPin=1
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)
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self.ethernet.host = self.platform.pci_host
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self.ethernet.pio = self.iobus.mem_side_ports
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self.ethernet.dma = self.iobus.cpu_side_ports
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if self.get_cache_hierarchy().is_ruby():
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for device in self._off_chip_devices + self._on_chip_devices:
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device.pio = self.iobus.mem_side_ports
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else:
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for device in self._off_chip_devices:
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device.pio = self.iobus.mem_side_ports
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for device in self._on_chip_devices:
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device.pio = self.get_cache_hierarchy().get_mem_side_port()
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self.bridge = Bridge(delay="10ns")
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self.bridge.mem_side_port = self.iobus.cpu_side_ports
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self.bridge.cpu_side_port = (
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self.get_cache_hierarchy().get_mem_side_port()
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)
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self.bridge.ranges = [
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AddrRange(dev.pio_addr, size=dev.pio_size)
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for dev in self._off_chip_devices
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]
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# PCI
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self.bridge.ranges.append(AddrRange(0x2F000000, size="16MB"))
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self.bridge.ranges.append(AddrRange(0x30000000, size="256MB"))
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self.bridge.ranges.append(AddrRange(0x40000000, size="512MB"))
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def _setup_pma(self) -> None:
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"""Set the PMA devices on each core."""
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uncacheable_range = [
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AddrRange(dev.pio_addr, size=dev.pio_size)
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for dev in self._on_chip_devices + self._off_chip_devices
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]
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# PCI
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uncacheable_range.append(AddrRange(0x2F000000, size="16MB"))
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uncacheable_range.append(AddrRange(0x30000000, size="256MB"))
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uncacheable_range.append(AddrRange(0x40000000, size="512MB"))
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# TODO: Not sure if this should be done per-core like in the example
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for cpu in self.get_processor().get_cores():
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cpu.get_mmu().pma_checker = PMAChecker(
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uncacheable=uncacheable_range
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)
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@overrides(AbstractSystemBoard)
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def has_dma_ports(self) -> bool:
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return False
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@overrides(AbstractSystemBoard)
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def get_dma_ports(self) -> List[Port]:
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raise NotImplementedError(
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"RISCVBoard does not have DMA Ports. "
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"Use `has_dma_ports()` to check this."
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)
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@overrides(AbstractSystemBoard)
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def has_io_bus(self) -> bool:
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return True
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@overrides(AbstractSystemBoard)
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def get_io_bus(self) -> IOXBar:
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return self.iobus
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@overrides(AbstractSystemBoard)
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def has_coherent_io(self) -> bool:
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return True
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@overrides(AbstractSystemBoard)
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def get_mem_side_coherent_io_port(self) -> Port:
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return self.iobus.mem_side_ports
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@overrides(AbstractSystemBoard)
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def _setup_memory_ranges(self):
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memory = self.get_memory()
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mem_size = memory.get_size()
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self.mem_ranges = [AddrRange(start=0x80000000, size=mem_size)]
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memory.set_memory_range(self.mem_ranges)
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def generate_device_tree(self, outdir: str) -> None:
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"""Creates the ``dtb`` and ``dts`` files.
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Creates two files in the outdir: ``device.dtb`` and ``device.dts``.
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:param outdir: Directory to output the files.
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"""
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state = FdtState(addr_cells=2, size_cells=2, cpu_cells=1)
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root = FdtNode("/")
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root.append(state.addrCellsProperty())
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root.append(state.sizeCellsProperty())
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root.appendCompatible(["riscv-virtio"])
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for mem_range in self.mem_ranges:
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node = FdtNode(f"memory@{int(mem_range.start):x}")
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node.append(FdtPropertyStrings("device_type", ["memory"]))
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node.append(
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FdtPropertyWords(
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"reg",
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state.addrCells(mem_range.start)
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+ state.sizeCells(mem_range.size()),
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)
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)
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root.append(node)
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node = FdtNode(f"chosen")
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bootargs = self.workload.command_line
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node.append(FdtPropertyStrings("bootargs", [bootargs]))
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node.append(FdtPropertyStrings("stdout-path", ["/uart@10000000"]))
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root.append(node)
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# See Documentation/devicetree/bindings/riscv/cpus.txt for details.
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cpus_node = FdtNode("cpus")
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cpus_state = FdtState(addr_cells=1, size_cells=0)
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cpus_node.append(cpus_state.addrCellsProperty())
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cpus_node.append(cpus_state.sizeCellsProperty())
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# Used by the CLINT driver to set the timer frequency. Value taken from
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# RISC-V kernel docs (Note: freedom-u540 is actually 1MHz)
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cpus_node.append(FdtPropertyWords("timebase-frequency", [100000000]))
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for i, core in enumerate(self.get_processor().get_cores()):
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node = FdtNode(f"cpu@{i}")
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node.append(FdtPropertyStrings("device_type", "cpu"))
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node.append(FdtPropertyWords("reg", state.CPUAddrCells(i)))
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node.append(FdtPropertyStrings("mmu-type", "riscv,sv48"))
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if core.core.isa[0].enable_Zicbom_fs.value:
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node.append(
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FdtPropertyWords(
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"riscv,cbom-block-size", self.get_cache_line_size()
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)
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)
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if core.core.isa[0].enable_Zicboz_fs.value:
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node.append(
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FdtPropertyWords(
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"riscv,cboz-block-size", self.get_cache_line_size()
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)
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)
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node.append(FdtPropertyStrings("status", "okay"))
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node.append(
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FdtPropertyStrings(
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"riscv,isa", core.core.isa[0].get_isa_string()
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)
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)
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# TODO: Should probably get this from the core.
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freq = self.clk_domain.clock[0].frequency
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node.append(FdtPropertyWords("clock-frequency", freq))
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node.appendCompatible(["riscv"])
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int_phandle = state.phandle(f"cpu@{i}.int_state")
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node.appendPhandle(f"cpu@{i}")
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int_node = FdtNode("interrupt-controller")
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int_state = FdtState(interrupt_cells=1)
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int_phandle = int_state.phandle(f"cpu@{i}.int_state")
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int_node.append(int_state.interruptCellsProperty())
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int_node.append(FdtProperty("interrupt-controller"))
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int_node.appendCompatible("riscv,cpu-intc")
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int_node.append(FdtPropertyWords("phandle", [int_phandle]))
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node.append(int_node)
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cpus_node.append(node)
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root.append(cpus_node)
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soc_node = FdtNode("soc")
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soc_state = FdtState(addr_cells=2, size_cells=2)
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soc_node.append(soc_state.addrCellsProperty())
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soc_node.append(soc_state.sizeCellsProperty())
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soc_node.append(FdtProperty("ranges"))
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soc_node.appendCompatible(["simple-bus"])
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# CLINT node
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clint = self.platform.clint
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clint_node = clint.generateBasicPioDeviceNode(
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soc_state, "clint", clint.pio_addr, clint.pio_size
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)
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int_extended = list()
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for i, core in enumerate(self.get_processor().get_cores()):
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phandle = soc_state.phandle(f"cpu@{i}.int_state")
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int_extended.append(phandle)
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int_extended.append(0x3)
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int_extended.append(phandle)
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int_extended.append(0x7)
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clint_node.append(
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FdtPropertyWords("interrupts-extended", int_extended)
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)
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clint_node.appendCompatible(["riscv,clint0"])
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soc_node.append(clint_node)
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# PLIC node
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plic = self.platform.plic
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plic_node = plic.generateBasicPioDeviceNode(
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soc_state, "plic", plic.pio_addr, plic.pio_size
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)
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int_state = FdtState(addr_cells=0, interrupt_cells=1)
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plic_node.append(int_state.addrCellsProperty())
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plic_node.append(int_state.interruptCellsProperty())
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phandle = int_state.phandle(plic)
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plic_node.append(FdtPropertyWords("phandle", [phandle]))
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plic_node.append(FdtPropertyWords("riscv,ndev", [plic.n_src - 1]))
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int_extended = list()
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cpu_id = 0
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phandle = int_state.phandle(f"cpu@{cpu_id}.int_state")
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for c in plic.hart_config:
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if c == ",":
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cpu_id += 1
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assert cpu_id < self.get_processor().get_num_cores()
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phandle = int_state.phandle(f"cpu@{cpu_id}.int_state")
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elif c == "S":
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int_extended.append(phandle)
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int_extended.append(0x9)
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elif c == "M":
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int_extended.append(phandle)
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int_extended.append(0xB)
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plic_node.append(FdtPropertyWords("interrupts-extended", int_extended))
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plic_node.append(FdtProperty("interrupt-controller"))
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plic_node.appendCompatible(["riscv,plic0"])
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soc_node.append(plic_node)
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# PCI
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pci_state = FdtState(
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addr_cells=3, size_cells=2, cpu_cells=1, interrupt_cells=1
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)
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pci_node = FdtNode("pci")
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if int(self.platform.pci_host.conf_device_bits) == 8:
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pci_node.appendCompatible("pci-host-cam-generic")
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elif int(self.platform.pci_host.conf_device_bits) == 12:
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pci_node.appendCompatible("pci-host-ecam-generic")
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else:
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m5.fatal("No compatibility string for the set conf_device_width")
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pci_node.append(FdtPropertyStrings("device_type", ["pci"]))
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# Cell sizes of child nodes/peripherals
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pci_node.append(pci_state.addrCellsProperty())
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pci_node.append(pci_state.sizeCellsProperty())
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pci_node.append(pci_state.interruptCellsProperty())
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# PCI address for CPU
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pci_node.append(
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FdtPropertyWords(
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"reg",
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soc_state.addrCells(self.platform.pci_host.conf_base)
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+ soc_state.sizeCells(self.platform.pci_host.conf_size),
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)
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)
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# Ranges mapping
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# For now some of this is hard coded, because the PCI module does not
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# have a proper full understanding of the memory map, but adapting the
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# PCI module is beyond the scope of what I'm trying to do here.
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# Values are taken from the ARM VExpress_GEM5_V1 platform.
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ranges = []
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# Pio address range
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ranges += self.platform.pci_host.pciFdtAddr(space=1, addr=0)
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ranges += soc_state.addrCells(self.platform.pci_host.pci_pio_base)
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ranges += pci_state.sizeCells(0x10000) # Fixed size
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# AXI memory address range
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ranges += self.platform.pci_host.pciFdtAddr(space=2, addr=0)
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ranges += soc_state.addrCells(self.platform.pci_host.pci_mem_base)
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ranges += pci_state.sizeCells(0x40000000) # Fixed size
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pci_node.append(FdtPropertyWords("ranges", ranges))
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# Interrupt mapping
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plic_handle = int_state.phandle(plic)
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int_base = self.platform.pci_host.int_base
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interrupts = []
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for i in range(int(self.platform.pci_host.int_count)):
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interrupts += self.platform.pci_host.pciFdtAddr(
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device=i, addr=0
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) + [int(i) + 1, plic_handle, int(int_base) + i]
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pci_node.append(FdtPropertyWords("interrupt-map", interrupts))
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int_count = int(self.platform.pci_host.int_count)
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if int_count & (int_count - 1):
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fatal("PCI interrupt count should be power of 2")
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intmask = self.platform.pci_host.pciFdtAddr(
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device=int_count - 1, addr=0
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) + [0x0]
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pci_node.append(FdtPropertyWords("interrupt-map-mask", intmask))
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if self.platform.pci_host._dma_coherent:
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pci_node.append(FdtProperty("dma-coherent"))
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soc_node.append(pci_node)
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# UART node
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uart = self.platform.uart
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uart_node = uart.generateBasicPioDeviceNode(
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soc_state, "uart", uart.pio_addr, uart.pio_size
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)
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uart_node.append(
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FdtPropertyWords("interrupts", [self.platform.uart_int_id])
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)
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uart_node.append(FdtPropertyWords("clock-frequency", [0x384000]))
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uart_node.append(
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FdtPropertyWords("interrupt-parent", soc_state.phandle(plic))
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)
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uart_node.appendCompatible(["ns8250", "ns16550a"])
|
|
soc_node.append(uart_node)
|
|
|
|
# VirtIO MMIO disk node
|
|
disk = self.disk
|
|
disk_node = disk.generateBasicPioDeviceNode(
|
|
soc_state, "virtio_mmio", disk.pio_addr, disk.pio_size
|
|
)
|
|
disk_node.append(FdtPropertyWords("interrupts", [disk.interrupt_id]))
|
|
disk_node.append(
|
|
FdtPropertyWords("interrupt-parent", soc_state.phandle(plic))
|
|
)
|
|
disk_node.appendCompatible(["virtio,mmio"])
|
|
soc_node.append(disk_node)
|
|
|
|
# VirtIO MMIO rng node
|
|
rng = self.rng
|
|
rng_node = rng.generateBasicPioDeviceNode(
|
|
soc_state, "virtio_mmio", rng.pio_addr, rng.pio_size
|
|
)
|
|
rng_node.append(FdtPropertyWords("interrupts", [rng.interrupt_id]))
|
|
rng_node.append(
|
|
FdtPropertyWords("interrupt-parent", soc_state.phandle(plic))
|
|
)
|
|
rng_node.appendCompatible(["virtio,mmio"])
|
|
soc_node.append(rng_node)
|
|
|
|
root.append(soc_node)
|
|
|
|
fdt = Fdt()
|
|
fdt.add_rootnode(root)
|
|
fdt.writeDtsFile(os.path.join(outdir, "device.dts"))
|
|
fdt.writeDtbFile(os.path.join(outdir, "device.dtb"))
|
|
|
|
@overrides(KernelDiskWorkload)
|
|
def get_disk_device(self):
|
|
return "/dev/vda"
|
|
|
|
@overrides(AbstractSystemBoard)
|
|
def _pre_instantiate(self):
|
|
if len(self._bootloader) > 0:
|
|
self.workload.bootloader_addr = 0x0
|
|
self.workload.bootloader_filename = self._bootloader[0]
|
|
self.workload.kernel_addr = 0x80200000
|
|
self.workload.entry_point = 0x80000000 # Bootloader starting point
|
|
else:
|
|
self.workload.kernel_addr = 0x0
|
|
self.workload.entry_point = 0x80000000
|
|
self._connect_things()
|
|
|
|
@overrides(KernelDiskWorkload)
|
|
def _add_disk_to_board(self, disk_image: AbstractResource):
|
|
image = CowDiskImage(
|
|
child=RawDiskImage(read_only=True), read_only=False
|
|
)
|
|
image.child.image_file = disk_image.get_local_path()
|
|
self.disk.vio.image = image
|
|
|
|
# Note: The below is a bit of a hack. We need to wait to generate the
|
|
# device tree until after the disk is set up. Now that the disk and
|
|
# workload are set, we can generate the device tree file.
|
|
self._setup_io_devices()
|
|
self._setup_pma()
|
|
|
|
# Default DTB address if bbl is built with --with-dts option
|
|
self.workload.dtb_addr = 0x87E00000
|
|
|
|
self.generate_device_tree(m5.options.outdir)
|
|
self.workload.dtb_filename = os.path.join(
|
|
m5.options.outdir, "device.dtb"
|
|
)
|
|
|
|
@overrides(KernelDiskWorkload)
|
|
def get_default_kernel_args(self) -> List[str]:
|
|
return [
|
|
"console=ttyS0",
|
|
"root={root_value}",
|
|
"disk_device={disk_device}",
|
|
"rw",
|
|
]
|