bcf455755e
Update the PLIC based on the [riscv-plic-spec](https://github.com/riscv/riscv-plic-spec) in the PR: - Support customized PLIC hardID and privilege mode configuration - Backward compatable with the n_contexts parameter, will generate the config like {0,M}, {0,S}, {1,M} ... Change-Id: Ibff736827edb7c97921e01fa27f503574a27a562
127 lines
5.0 KiB
Python
127 lines
5.0 KiB
Python
# Copyright (c) 2021 Huawei International
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# Copyright (c) 2023 Google LLC
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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from m5.objects.Device import BasicPioDevice
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from m5.params import *
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from m5.proxy import *
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from m5.util.fdthelper import *
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class PlicBase(BasicPioDevice):
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"""
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This is abstract class of PLIC and
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define interface to handle received
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interrupt singal from device
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"""
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type = "PlicBase"
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cxx_header = "dev/riscv/plic.hh"
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cxx_class = "gem5::PlicBase"
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abstract = True
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pio_size = Param.Addr("PIO Size")
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class Plic(PlicBase):
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"""
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This implementation of PLIC is based on
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the riscv-plic-spec repository:
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https://github.com/riscv/riscv-plic-spec/releases/tag/1.0.0
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"""
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type = "Plic"
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cxx_header = "dev/riscv/plic.hh"
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cxx_class = "gem5::Plic"
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pio_size = 0x4000000
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n_src = Param.Int("Number of interrupt sources")
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# Ref: https://github.com/qemu/qemu/blob/760b4dc/hw/intc/sifive_plic.c#L285
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hart_config = Param.String(
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"",
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"String represent for PLIC hart/pmode config like QEMU plic"
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"Ex."
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"'M' 1 hart with M mode"
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"'MS,MS' 2 harts, 0-1 with M and S mode"
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"'M,MS,MS,MS,MS' 5 harts, 0 with M mode, 1-5 with M and S mode",
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)
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n_contexts = Param.Int(
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0,
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"Deprecated, use `hart_config` instead. "
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"Number of interrupt contexts. Usually the number "
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"of threads * 2. One for M mode, one for S mode",
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)
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def generateDeviceTree(self, state):
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node = self.generateBasicPioDeviceNode(
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state, "plic", self.pio_addr, self.pio_size
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)
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int_state = FdtState(addr_cells=0, interrupt_cells=1)
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node.append(int_state.addrCellsProperty())
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node.append(int_state.interruptCellsProperty())
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phandle = int_state.phandle(self)
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node.append(FdtPropertyWords("phandle", [phandle]))
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node.append(FdtPropertyWords("riscv,ndev", [self.n_src - 1]))
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cpus = self.system.unproxy(self).cpu
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int_extended = list()
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if self.n_contexts != 0:
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for cpu in cpus:
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phandle = int_state.phandle(cpu)
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int_extended.append(phandle)
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int_extended.append(0xB)
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int_extended.append(phandle)
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int_extended.append(0x9)
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elif self.hart_config != "":
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cpu_id = 0
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phandle = int_state.phandle(cpus[cpu_id])
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for c in self.hart_config:
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if c == ",":
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cpu_id += 1
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phandle = int_state.phandle(cpus[cpu_id])
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elif c == "S":
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int_extended.append(phandle)
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int_extended.append(0x9)
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elif c == "M":
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int_extended.append(phandle)
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int_extended.append(0xB)
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node.append(FdtPropertyWords("interrupts-extended", int_extended))
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node.append(FdtProperty("interrupt-controller"))
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node.appendCompatible(["riscv,plic0"])
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yield node
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