bcf455755e
Update the PLIC based on the [riscv-plic-spec](https://github.com/riscv/riscv-plic-spec) in the PR: - Support customized PLIC hardID and privilege mode configuration - Backward compatable with the n_contexts parameter, will generate the config like {0,M}, {0,S}, {1,M} ... Change-Id: Ibff736827edb7c97921e01fa27f503574a27a562
268 lines
9.2 KiB
Python
Executable File
268 lines
9.2 KiB
Python
Executable File
# Copyright (c) 2021 Huawei International
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# Copyright (c) 2022 EXAscale Performance SYStems (EXAPSYS)
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# Copyright (c) 2023 Google LLC
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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from m5.objects.Clint import Clint
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from m5.objects.PciHost import GenericPciHost
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from m5.objects.Platform import Platform
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from m5.objects.Plic import Plic
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from m5.objects.PMAChecker import PMAChecker
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from m5.objects.RTC import RiscvRTC
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from m5.objects.Terminal import Terminal
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from m5.objects.Uart import RiscvUart8250
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from m5.params import *
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from m5.proxy import *
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from m5.util.fdthelper import *
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class GenericRiscvPciHost(GenericPciHost):
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type = "GenericRiscvPciHost"
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cxx_header = "dev/riscv/pci_host.hh"
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cxx_class = "gem5::GenericRiscvPciHost"
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int_base = Param.Int(
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0x10, "Base number used as interrupt line and PLIC source."
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)
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int_count = Param.Unsigned(
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4, "Maximum number of interrupts used by this host"
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)
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# This python parameter can be used in configuration scripts to turn
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# on/off the fdt dma-coherent flag when doing dtb autogeneration
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_dma_coherent = True
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class HiFiveBase(Platform):
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"""HiFive Base Abstract Platform
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Implementation:
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This is the base class for SiFive's HiFive
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board series. It contains the CLINT and PLIC
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interrupt controllers, Uart and Disk.
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Driving CLINT:
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CLINT has an interrupt pin which increments
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mtime. It can be connected to any interrupt
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source pin which acts as the RTCCLK pin. An
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abstract RTC wrapper called RiscvRTC can be
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used.
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Driving PLIC:
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PLIC handles external interrupts. Interrupt
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PioDevices should inherit from PlicIntDevice
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(PCI and DMA not yet implemented). It contains
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a parameter interrupt_id which should be used
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to call platform->postPciInt(id).
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All PLIC interrupt devices should be returned
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by _off_chip_devices().
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"""
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type = "HiFiveBase"
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cxx_header = "dev/riscv/hifive.hh"
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cxx_class = "gem5::HiFiveBase"
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# CLINT
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clint = Param.Clint(NULL, "CLINT")
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# PLIC
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plic = Param.PlicBase(NULL, "PLIC")
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# Int source ID to redirect console interrupts to
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# Set to 0 if using a pci interrupt for Uart instead
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uart_int_id = Param.Int(0, "PLIC Uart interrupt ID")
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def _on_chip_devices(self):
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"""Returns a list of on-chip peripherals"""
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return []
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def _off_chip_devices(self):
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"""Returns a list of off-chip peripherals"""
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return []
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def _on_chip_ranges(self):
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"""Returns a list of on-chip peripherals
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address range
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"""
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return [
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AddrRange(dev.pio_addr, size=dev.pio_size)
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for dev in self._on_chip_devices()
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]
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def _off_chip_ranges(self):
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"""Returns a list of off-chip peripherals
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address range
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"""
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return [
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AddrRange(dev.pio_addr, size=dev.pio_size)
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for dev in self._off_chip_devices()
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]
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def attachOnChipIO(self, bus):
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"""Attach on-chip IO devices, needs modification
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to support DMA
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"""
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for device in self._on_chip_devices():
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device.pio = bus.mem_side_ports
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def attachOffChipIO(self, bus):
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"""Attach off-chip IO devices, needs modification
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to support DMA
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"""
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for device in self._off_chip_devices():
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device.pio = bus.mem_side_ports
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class HiFive(HiFiveBase):
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"""HiFive Platform
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Implementation:
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Implementation details are based on SiFive
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FU540-C000. https://sifive.cdn.prismic.io/
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sifive/b5e7a29c-d3c2-44ea-85fb-acc1df282e2
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1_FU540-C000-v1p3.pdf
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Setup:
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The following sections outline the required
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setup for a RISC-V HiFive platform. See
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configs/example/riscv/fs_linux.py for example.
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Uart:
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The HiFive platform also has an uart_int_id.
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This is because Uart8250 uses postConsoleInt
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instead of postPciInt. In the future if a Uart
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that inherits PlicIntDevice is implemented,
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this can be removed.
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Disk:
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See fs_linux.py for setup example.
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PMAChecker:
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The PMAChecker will be attached to the MMU of
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each CPU (which allows them to differ). See
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fs_linux.py for setup example.
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"""
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# CLINT
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clint = Clint(pio_addr=0x2000000)
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# PLIC
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plic = Plic(pio_addr=0xC000000)
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# PCI
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pci_host = GenericRiscvPciHost(
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conf_base=0x30000000,
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conf_size="256MB",
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conf_device_bits=12,
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pci_pio_base=0x2F000000,
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pci_mem_base=0x40000000,
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)
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# Uart
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uart = RiscvUart8250(pio_addr=0x10000000)
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# Int source ID to redirect console interrupts to
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# Set to 0 if using a pci interrupt for Uart instead
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uart_int_id = 0xA
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terminal = Terminal()
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def _on_chip_devices(self):
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"""Returns a list of on-chip peripherals"""
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return [self.clint, self.plic]
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def _off_chip_devices(self):
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"""Returns a list of off-chip peripherals"""
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devices = [self.uart]
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if hasattr(self, "disk"):
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devices.append(self.disk)
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if hasattr(self, "rng"):
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devices.append(self.rng)
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return devices
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def attachPlic(self):
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"""Count and set number of PLIC interrupt sources"""
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plic_srcs = [
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self.uart_int_id,
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self.pci_host.int_base + self.pci_host.int_count,
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]
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for device in self._off_chip_devices():
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if hasattr(device, "interrupt_id"):
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plic_srcs.append(device.interrupt_id)
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self.plic.n_src = max(plic_srcs) + 1
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def setNumCores(self, num_cpu):
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"""Sets the CLINT to number of threads and the PLIC hartID/pmode for
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each contexts. Assumes that the cores have a single hardware thread.
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"""
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self.plic.hart_config = ",".join(["MS" for _ in range(num_cpu)])
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self.clint.num_threads = num_cpu
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def generateDeviceTree(self, state):
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cpus_node = FdtNode("cpus")
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cpus_node.append(FdtPropertyWords("timebase-frequency", [10000000]))
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yield cpus_node
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node = FdtNode("soc")
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local_state = FdtState(addr_cells=2, size_cells=2)
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node.append(local_state.addrCellsProperty())
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node.append(local_state.sizeCellsProperty())
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node.append(FdtProperty("ranges"))
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node.appendCompatible(["simple-bus"])
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for subnode in self.recurseDeviceTree(local_state):
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node.append(subnode)
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yield node
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# For generating devicetree
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_cpu_count = 0
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def annotateCpuDeviceNode(self, cpu, state):
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cpu.append(FdtPropertyStrings("mmu-type", "riscv,sv48"))
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cpu.append(FdtPropertyStrings("status", "okay"))
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cpu.append(FdtPropertyStrings("riscv,isa", "rv64imafdc"))
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cpu.appendCompatible(["riscv"])
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int_node = FdtNode("interrupt-controller")
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int_state = FdtState(interrupt_cells=1)
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int_node.append(int_state.interruptCellsProperty())
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int_node.append(FdtProperty("interrupt-controller"))
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int_node.appendCompatible("riscv,cpu-intc")
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cpus = self.system.unproxy(self).cpu
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phandle = int_state.phandle(cpus[self._cpu_count])
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self._cpu_count += 1
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int_node.append(FdtPropertyWords("phandle", [phandle]))
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cpu.append(int_node)
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