Further renames/reorganization will be coming shortly; what is currently CPUExecContext (the old ExecContext from m5) will be renamed to SimpleThread or something similar.
src/arch/alpha/arguments.cc:
src/arch/alpha/arguments.hh:
src/arch/alpha/ev5.cc:
src/arch/alpha/faults.cc:
src/arch/alpha/faults.hh:
src/arch/alpha/freebsd/system.cc:
src/arch/alpha/freebsd/system.hh:
src/arch/alpha/isa/branch.isa:
src/arch/alpha/isa/decoder.isa:
src/arch/alpha/isa/main.isa:
src/arch/alpha/linux/process.cc:
src/arch/alpha/linux/system.cc:
src/arch/alpha/linux/system.hh:
src/arch/alpha/linux/threadinfo.hh:
src/arch/alpha/process.cc:
src/arch/alpha/regfile.hh:
src/arch/alpha/stacktrace.cc:
src/arch/alpha/stacktrace.hh:
src/arch/alpha/tlb.cc:
src/arch/alpha/tlb.hh:
src/arch/alpha/tru64/process.cc:
src/arch/alpha/tru64/system.cc:
src/arch/alpha/tru64/system.hh:
src/arch/alpha/utility.hh:
src/arch/alpha/vtophys.cc:
src/arch/alpha/vtophys.hh:
src/arch/mips/faults.cc:
src/arch/mips/faults.hh:
src/arch/mips/isa_traits.cc:
src/arch/mips/isa_traits.hh:
src/arch/mips/linux/process.cc:
src/arch/mips/process.cc:
src/arch/mips/regfile/float_regfile.hh:
src/arch/mips/regfile/int_regfile.hh:
src/arch/mips/regfile/misc_regfile.hh:
src/arch/mips/regfile/regfile.hh:
src/arch/mips/stacktrace.hh:
src/arch/sparc/faults.cc:
src/arch/sparc/faults.hh:
src/arch/sparc/isa_traits.hh:
src/arch/sparc/linux/process.cc:
src/arch/sparc/linux/process.hh:
src/arch/sparc/process.cc:
src/arch/sparc/regfile.hh:
src/arch/sparc/solaris/process.cc:
src/arch/sparc/stacktrace.hh:
src/arch/sparc/ua2005.cc:
src/arch/sparc/utility.hh:
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
src/base/remote_gdb.cc:
src/base/remote_gdb.hh:
src/cpu/base.cc:
src/cpu/base.hh:
src/cpu/base_dyn_inst.hh:
src/cpu/checker/cpu.cc:
src/cpu/checker/cpu.hh:
src/cpu/checker/exec_context.hh:
src/cpu/cpu_exec_context.cc:
src/cpu/cpu_exec_context.hh:
src/cpu/cpuevent.cc:
src/cpu/cpuevent.hh:
src/cpu/exetrace.hh:
src/cpu/intr_control.cc:
src/cpu/memtest/memtest.hh:
src/cpu/o3/alpha_cpu.hh:
src/cpu/o3/alpha_cpu_impl.hh:
src/cpu/o3/alpha_dyn_inst_impl.hh:
src/cpu/o3/commit.hh:
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/regfile.hh:
src/cpu/o3/thread_state.hh:
src/cpu/ozone/back_end.hh:
src/cpu/ozone/cpu.hh:
src/cpu/ozone/cpu_impl.hh:
src/cpu/ozone/front_end.hh:
src/cpu/ozone/front_end_impl.hh:
src/cpu/ozone/inorder_back_end.hh:
src/cpu/ozone/lw_back_end.hh:
src/cpu/ozone/lw_back_end_impl.hh:
src/cpu/ozone/lw_lsq.hh:
src/cpu/ozone/lw_lsq_impl.hh:
src/cpu/ozone/thread_state.hh:
src/cpu/pc_event.cc:
src/cpu/pc_event.hh:
src/cpu/profile.cc:
src/cpu/profile.hh:
src/cpu/quiesce_event.cc:
src/cpu/quiesce_event.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/base.cc:
src/cpu/simple/base.hh:
src/cpu/simple/timing.cc:
src/cpu/static_inst.cc:
src/cpu/static_inst.hh:
src/cpu/thread_state.hh:
src/dev/alpha_console.cc:
src/dev/ns_gige.cc:
src/dev/sinic.cc:
src/dev/tsunami_cchip.cc:
src/kern/kernel_stats.cc:
src/kern/kernel_stats.hh:
src/kern/linux/events.cc:
src/kern/linux/events.hh:
src/kern/system_events.cc:
src/kern/system_events.hh:
src/kern/tru64/dump_mbuf.cc:
src/kern/tru64/tru64.hh:
src/kern/tru64/tru64_events.cc:
src/kern/tru64/tru64_events.hh:
src/mem/vport.cc:
src/mem/vport.hh:
src/sim/faults.cc:
src/sim/faults.hh:
src/sim/process.cc:
src/sim/process.hh:
src/sim/pseudo_inst.cc:
src/sim/pseudo_inst.hh:
src/sim/syscall_emul.cc:
src/sim/syscall_emul.hh:
src/sim/system.cc:
src/cpu/thread_context.hh:
src/sim/system.hh:
src/sim/vptr.hh:
Change ExecContext to ThreadContext.
--HG--
rename : src/cpu/exec_context.hh => src/cpu/thread_context.hh
extra : convert_revision : 108bb97d15a114a565a2a6a23faa554f4e2fd77e
356 lines
8.8 KiB
C++
356 lines
8.8 KiB
C++
/*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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* Kevin Lim
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*/
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#ifndef __ALPHA_FAULTS_HH__
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#define __ALPHA_FAULTS_HH__
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#include "arch/alpha/isa_traits.hh"
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#include "sim/faults.hh"
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// The design of the "name" and "vect" functions is in sim/faults.hh
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namespace AlphaISA
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{
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typedef const Addr FaultVect;
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class AlphaFault : public FaultBase
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{
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protected:
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virtual bool skipFaultingInstruction() {return false;}
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virtual bool setRestartAddress() {return true;}
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public:
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#if FULL_SYSTEM
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void invoke(ThreadContext * tc);
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#endif
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virtual FaultVect vect() = 0;
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virtual FaultStat & countStat() = 0;
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};
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class MachineCheckFault : public AlphaFault
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{
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private:
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static FaultName _name;
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static FaultVect _vect;
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static FaultStat _count;
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public:
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FaultName name() {return _name;}
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FaultVect vect() {return _vect;}
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FaultStat & countStat() {return _count;}
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bool isMachineCheckFault() {return true;}
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};
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class AlignmentFault : public AlphaFault
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{
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private:
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static FaultName _name;
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static FaultVect _vect;
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static FaultStat _count;
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public:
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FaultName name() {return _name;}
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FaultVect vect() {return _vect;}
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FaultStat & countStat() {return _count;}
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bool isAlignmentFault() {return true;}
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};
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static inline Fault genMachineCheckFault()
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{
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return new MachineCheckFault;
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}
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static inline Fault genAlignmentFault()
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{
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return new AlignmentFault;
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}
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class ResetFault : public AlphaFault
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{
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private:
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static FaultName _name;
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static FaultVect _vect;
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static FaultStat _count;
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public:
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FaultName name() {return _name;}
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FaultVect vect() {return _vect;}
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FaultStat & countStat() {return _count;}
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};
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class ArithmeticFault : public AlphaFault
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{
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protected:
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bool skipFaultingInstruction() {return true;}
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private:
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static FaultName _name;
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static FaultVect _vect;
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static FaultStat _count;
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public:
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FaultName name() {return _name;}
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FaultVect vect() {return _vect;}
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FaultStat & countStat() {return _count;}
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#if FULL_SYSTEM
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void invoke(ThreadContext * tc);
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#endif
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};
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class InterruptFault : public AlphaFault
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{
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protected:
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bool setRestartAddress() {return false;}
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private:
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static FaultName _name;
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static FaultVect _vect;
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static FaultStat _count;
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public:
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FaultName name() {return _name;}
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FaultVect vect() {return _vect;}
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FaultStat & countStat() {return _count;}
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};
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class DtbFault : public AlphaFault
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{
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#if FULL_SYSTEM
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private:
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AlphaISA::VAddr vaddr;
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uint32_t reqFlags;
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uint64_t flags;
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public:
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DtbFault(AlphaISA::VAddr _vaddr, uint32_t _reqFlags, uint64_t _flags)
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: vaddr(_vaddr), reqFlags(_reqFlags), flags(_flags)
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{ }
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#endif
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FaultName name() = 0;
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FaultVect vect() = 0;
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FaultStat & countStat() = 0;
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#if FULL_SYSTEM
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void invoke(ThreadContext * tc);
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#endif
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};
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class NDtbMissFault : public DtbFault
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{
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private:
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static FaultName _name;
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static FaultVect _vect;
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static FaultStat _count;
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public:
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#if FULL_SYSTEM
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NDtbMissFault(AlphaISA::VAddr vaddr, uint32_t reqFlags, uint64_t flags)
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: DtbFault(vaddr, reqFlags, flags)
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{ }
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#endif
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FaultName name() {return _name;}
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FaultVect vect() {return _vect;}
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FaultStat & countStat() {return _count;}
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};
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class PDtbMissFault : public DtbFault
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{
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private:
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static FaultName _name;
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static FaultVect _vect;
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static FaultStat _count;
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public:
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#if FULL_SYSTEM
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PDtbMissFault(AlphaISA::VAddr vaddr, uint32_t reqFlags, uint64_t flags)
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: DtbFault(vaddr, reqFlags, flags)
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{ }
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#endif
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FaultName name() {return _name;}
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FaultVect vect() {return _vect;}
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FaultStat & countStat() {return _count;}
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};
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class DtbPageFault : public DtbFault
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{
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private:
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static FaultName _name;
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static FaultVect _vect;
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static FaultStat _count;
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public:
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#if FULL_SYSTEM
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DtbPageFault(AlphaISA::VAddr vaddr, uint32_t reqFlags, uint64_t flags)
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: DtbFault(vaddr, reqFlags, flags)
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{ }
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#endif
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FaultName name() {return _name;}
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FaultVect vect() {return _vect;}
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FaultStat & countStat() {return _count;}
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};
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class DtbAcvFault : public DtbFault
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{
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private:
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static FaultName _name;
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static FaultVect _vect;
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static FaultStat _count;
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public:
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#if FULL_SYSTEM
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DtbAcvFault(AlphaISA::VAddr vaddr, uint32_t reqFlags, uint64_t flags)
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: DtbFault(vaddr, reqFlags, flags)
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{ }
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#endif
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FaultName name() {return _name;}
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FaultVect vect() {return _vect;}
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FaultStat & countStat() {return _count;}
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};
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class DtbAlignmentFault : public DtbFault
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{
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private:
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static FaultName _name;
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static FaultVect _vect;
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static FaultStat _count;
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public:
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#if FULL_SYSTEM
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DtbAlignmentFault(AlphaISA::VAddr vaddr, uint32_t reqFlags, uint64_t flags)
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: DtbFault(vaddr, reqFlags, flags)
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{ }
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#endif
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FaultName name() {return _name;}
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FaultVect vect() {return _vect;}
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FaultStat & countStat() {return _count;}
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};
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class ItbFault : public AlphaFault
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{
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private:
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Addr pc;
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public:
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ItbFault(Addr _pc)
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: pc(_pc)
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{ }
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FaultName name() = 0;
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FaultVect vect() = 0;
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FaultStat & countStat() = 0;
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#if FULL_SYSTEM
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void invoke(ThreadContext * tc);
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#endif
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};
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class ItbMissFault : public ItbFault
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{
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private:
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static FaultName _name;
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static FaultVect _vect;
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static FaultStat _count;
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public:
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ItbMissFault(Addr pc)
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: ItbFault(pc)
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{ }
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FaultName name() {return _name;}
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FaultVect vect() {return _vect;}
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FaultStat & countStat() {return _count;}
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};
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class ItbPageFault : public ItbFault
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{
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private:
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static FaultName _name;
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static FaultVect _vect;
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static FaultStat _count;
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public:
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ItbPageFault(Addr pc)
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: ItbFault(pc)
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{ }
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FaultName name() {return _name;}
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FaultVect vect() {return _vect;}
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FaultStat & countStat() {return _count;}
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};
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class ItbAcvFault : public ItbFault
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{
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private:
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static FaultName _name;
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static FaultVect _vect;
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static FaultStat _count;
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public:
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ItbAcvFault(Addr pc)
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: ItbFault(pc)
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{ }
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FaultName name() {return _name;}
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FaultVect vect() {return _vect;}
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FaultStat & countStat() {return _count;}
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};
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class UnimplementedOpcodeFault : public AlphaFault
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{
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private:
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static FaultName _name;
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static FaultVect _vect;
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static FaultStat _count;
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public:
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FaultName name() {return _name;}
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FaultVect vect() {return _vect;}
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FaultStat & countStat() {return _count;}
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};
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class FloatEnableFault : public AlphaFault
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{
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private:
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static FaultName _name;
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static FaultVect _vect;
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static FaultStat _count;
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public:
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FaultName name() {return _name;}
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FaultVect vect() {return _vect;}
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FaultStat & countStat() {return _count;}
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};
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class PalFault : public AlphaFault
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{
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protected:
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bool skipFaultingInstruction() {return true;}
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private:
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static FaultName _name;
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static FaultVect _vect;
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static FaultStat _count;
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public:
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FaultName name() {return _name;}
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FaultVect vect() {return _vect;}
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FaultStat & countStat() {return _count;}
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};
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class IntegerOverflowFault : public AlphaFault
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{
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private:
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static FaultName _name;
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static FaultVect _vect;
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static FaultStat _count;
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public:
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FaultName name() {return _name;}
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FaultVect vect() {return _vect;}
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FaultStat & countStat() {return _count;}
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};
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} // AlphaISA namespace
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#endif // __FAULTS_HH__
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