787204c92d
The command executed was `black src configs tests util`. Change-Id: I8dfaa6ab04658fea37618127d6ac19270028d771 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47024 Maintainer: Bobby Bruce <bbruce@ucdavis.edu> Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
67 lines
3.3 KiB
Python
67 lines
3.3 KiB
Python
# Copyright (c) 2012, 2017-2018 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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from m5 import fatal
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import m5.objects
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def config_etrace(cpu_cls, cpu_list, options):
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if issubclass(cpu_cls, m5.objects.DerivO3CPU):
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# Assign the same file name to all cpus for now. This must be
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# revisited when creating elastic traces for multi processor systems.
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for cpu in cpu_list:
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# Attach the elastic trace probe listener. Set the protobuf trace
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# file names. Set the dependency window size equal to the cpu it
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# is attached to.
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cpu.traceListener = m5.objects.ElasticTrace(
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instFetchTraceFile=options.inst_trace_file,
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dataDepTraceFile=options.data_trace_file,
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depWindowSize=3 * cpu.numROBEntries,
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)
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# Make the number of entries in the ROB, LQ and SQ very
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# large so that there are no stalls due to resource
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# limitation as such stalls will get captured in the trace
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# as compute delay. For replay, ROB, LQ and SQ sizes are
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# modelled in the Trace CPU.
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cpu.numROBEntries = 512
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cpu.LQEntries = 128
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cpu.SQEntries = 128
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else:
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fatal(
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"%s does not support data dependency tracing. Use a CPU model of"
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" type or inherited from DerivO3CPU.",
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cpu_cls,
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)
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