996f0ce168
The only difference between the RiscvUart8250 and the regular Uart8250 is that the Riscv version knows how to generate a device tree node appropriate for use in a Riscv system. This lets us drop the TARGET_ISA check from that method, since that should be called iff the target system is Riscv. Also update the HiFive platform to use the RiscvUart8250 so that it can continue to generate device trees successfully. Change-Id: I306596efffed5e5eed337d3db492d2782ebfaa8d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52144 Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Maintainer: Jason Lowe-Power <power.jg@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
84 lines
3.7 KiB
Python
84 lines
3.7 KiB
Python
# Copyright (c) 2018 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Copyright (c) 2005-2007 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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from m5.params import *
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from m5.proxy import *
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from m5.util.fdthelper import *
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from m5.defines import buildEnv
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from m5.objects.Device import BasicPioDevice
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from m5.objects.Serial import SerialDevice
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class Uart(BasicPioDevice):
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type = 'Uart'
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abstract = True
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cxx_header = "dev/serial/uart.hh"
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cxx_class = 'gem5::Uart'
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platform = Param.Platform(Parent.any, "Platform this device is part of.")
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device = Param.SerialDevice(Parent.any, "The terminal")
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class SimpleUart(Uart):
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type = 'SimpleUart'
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cxx_header = "dev/serial/simple.hh"
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cxx_class = 'gem5::SimpleUart'
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byte_order = Param.ByteOrder("little", "Device byte order")
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pio_size = Param.Addr(0x4, "Size of address range")
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end_on_eot = Param.Bool(False, "End the simulation when a EOT is "\
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"received on the UART")
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class Uart8250(Uart):
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type = 'Uart8250'
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cxx_header = "dev/serial/uart8250.hh"
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cxx_class = 'gem5::Uart8250'
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pio_size = Param.Addr(0x8, "Size of address range")
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class RiscvUart8250(Uart8250):
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def generateDeviceTree(self, state):
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node = self.generateBasicPioDeviceNode(
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state, "uart", self.pio_addr, self.pio_size)
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platform = self.platform.unproxy(self)
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plic = platform.plic
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node.append(
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FdtPropertyWords("interrupts", [platform.uart_int_id]))
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node.append(
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FdtPropertyWords("clock-frequency", [0x384000]))
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node.append(
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FdtPropertyWords("interrupt-parent", state.phandle(plic)))
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node.appendCompatible(["ns8250"])
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yield node
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