Wade Walker e6672d1f29 ARM: Add two unimplemented miscellaneous registers. ...

Adds MISCREG_ID_MMFR2 and removes break on access to MISCREG_CLIDR. Both
registers now return values that are consistent with current ARM
implementations.

2011-07-15 11:53:34 -05:00

..

arch

ARM: Add two unimplemented miscellaneous registers.

2011-07-15 11:53:34 -05:00

base

Loader: Handle bad section names when loading an ELF file.

2011-06-12 23:52:21 -07:00

cpu

Branch predictor: Fixes the tournament branch predictor.

2011-07-10 12:56:08 -05:00

dev

IO: Handle case where ISA Fake device is being used as a fake memory.

2011-07-10 12:56:08 -05:00

doxygen

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kern

scons: rename TraceFlags to DebugFlags

2011-06-02 17:36:21 -07:00

mem

ruby: added generic dma machine

2011-07-06 18:45:15 -07:00

python

O3: Make sure fetch doesn't go off into the weeds during speculation.

2011-07-10 12:56:08 -05:00

sim

O3: Make sure fetch doesn't go off into the weeds during speculation.

2011-07-10 12:56:08 -05:00

unittest

copyright: clean up copyright blocks

2011-06-02 14:36:35 -07:00

Doxyfile

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SConscript

scons: rename TraceFlags to DebugFlags

2011-06-02 17:36:21 -07:00