e6604bf109
This is basic abstract platform and all of RISC-V system should use platform inherit from HiFiveBase, HiFiveBase declared the common way to handle interrupt. Change-Id: I52122e1c82c200d7e6012433c2535c07d427f637 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68199 Maintainer: Jason Lowe-Power <power.jg@gmail.com> Reviewed-by: Yu-hsin Wang <yuhsingw@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
95 lines
2.9 KiB
C++
95 lines
2.9 KiB
C++
/*
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* Copyright (c) 2021 Huawei International
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* Copyright (c) 2023 Google LLC
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "dev/riscv/hifive.hh"
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#include "dev/riscv/clint.hh"
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#include "dev/riscv/plic.hh"
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#include "params/HiFiveBase.hh"
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#include "sim/system.hh"
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namespace gem5
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{
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using namespace RiscvISA;
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HiFiveBase::HiFiveBase(const Params ¶ms) :
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Platform(params),
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clint(params.clint), plic(params.plic),
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uartIntID(params.uart_int_id)
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{
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fatal_if(clint == nullptr, "CLINT should not be NULL");
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fatal_if(plic == nullptr, "PLIC should not be NULL");
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}
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void
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HiFiveBase::postConsoleInt()
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{
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plic->post(uartIntID);
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}
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void
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HiFiveBase::clearConsoleInt()
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{
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plic->clear(uartIntID);
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}
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void
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HiFiveBase::postPciInt(int line)
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{
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plic->post(line);
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}
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void
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HiFiveBase::clearPciInt(int line)
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{
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plic->clear(line);
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}
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void
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HiFiveBase::serialize(CheckpointOut &cp) const
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{
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}
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void
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HiFiveBase::unserialize(CheckpointIn &cp)
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{
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}
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} // namespace gem5
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