e57205f539
Change-Id: I6bb7a4f78e59082c3f783a5d4c2cb79f9c6df61f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49773 Reviewed-by: Boris Shingarov <shingarov@labware.com> Maintainer: Gabe Black <gabe.black@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
495 lines
20 KiB
C++
495 lines
20 KiB
C++
/*
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* Copyright (c) 2021 Huawei International
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* Copyright 2015 LabWare
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* Copyright 2014 Google, Inc.
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* Copyright (c) 2010 ARM Limited
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* Copyright (c) 2020 Barkhausen Institut
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2017 The University of Virginia
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 1990, 1993 The Regents of the University of California
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* All rights reserved
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*
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* This software was developed by the Computer Systems Engineering group
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* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
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* contributed to Berkeley.
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*
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* All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Lawrence Berkeley Laboratories.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)kgdb_stub.c 8.4 (Berkeley) 1/12/94
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*/
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/*-
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* Copyright (c) 2001 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* $NetBSD: kgdb_stub.c,v 1.8 2001/07/07 22:58:00 wdk Exp $
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*
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* Taken from NetBSD
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*
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* "Stub" to allow remote cpu to debug over a serial line using gdb.
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*/
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#include "arch/riscv/remote_gdb.hh"
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#include <string>
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#include "arch/riscv/gdb-xml/gdb_xml_riscv_cpu.hh"
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#include "arch/riscv/gdb-xml/gdb_xml_riscv_csr.hh"
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#include "arch/riscv/gdb-xml/gdb_xml_riscv_fpu.hh"
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#include "arch/riscv/gdb-xml/gdb_xml_riscv_target.hh"
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#include "arch/riscv/mmu.hh"
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#include "arch/riscv/pagetable_walker.hh"
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#include "arch/riscv/regs/float.hh"
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#include "arch/riscv/regs/int.hh"
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#include "arch/riscv/regs/misc.hh"
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#include "arch/riscv/tlb.hh"
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#include "cpu/thread_state.hh"
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#include "debug/GDBAcc.hh"
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#include "mem/page_table.hh"
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#include "sim/full_system.hh"
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namespace gem5
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{
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using namespace RiscvISA;
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RemoteGDB::RemoteGDB(System *_system, int _port)
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: BaseRemoteGDB(_system, _port), regCache(this)
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{
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}
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bool
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RemoteGDB::acc(Addr va, size_t len)
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{
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if (FullSystem)
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{
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MMU *mmu = static_cast<MMU *>(context()->getMMUPtr());
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unsigned logBytes;
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Addr paddr = va;
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PrivilegeMode pmode = mmu->getMemPriv(context(), BaseMMU::Read);
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SATP satp = context()->readMiscReg(MISCREG_SATP);
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if (pmode != PrivilegeMode::PRV_M &&
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satp.mode != AddrXlateMode::BARE) {
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Walker *walker = mmu->getDataWalker();
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Fault fault = walker->startFunctional(
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context(), paddr, logBytes, BaseMMU::Read);
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if (fault != NoFault)
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return false;
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}
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return true;
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}
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return context()->getProcessPtr()->pTable->lookup(va) != nullptr;
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}
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void
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RemoteGDB::RiscvGdbRegCache::getRegs(ThreadContext *context)
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{
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DPRINTF(GDBAcc, "getregs in remotegdb, size %lu\n", size());
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// General registers
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for (int i = 0; i < int_reg::NumArchRegs; i++) {
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r.gpr[i] = context->getReg(RegId(IntRegClass, i));
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}
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r.pc = context->pcState().instAddr();
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// Floating point registers
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for (int i = 0; i < float_reg::NumRegs; i++)
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r.fpu[i] = context->getReg(RegId(FloatRegClass, i));
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r.fflags = context->readMiscRegNoEffect(
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CSRData.at(CSR_FFLAGS).physIndex) & CSRMasks.at(CSR_FFLAGS);
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r.frm = context->readMiscRegNoEffect(
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CSRData.at(CSR_FRM).physIndex) & CSRMasks.at(CSR_FRM);
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r.fcsr = context->readMiscRegNoEffect(
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CSRData.at(CSR_FCSR).physIndex) & CSRMasks.at(CSR_FCSR);
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// CSR registers
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r.cycle = context->readMiscRegNoEffect(
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CSRData.at(CSR_CYCLE).physIndex);
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r.time = context->readMiscRegNoEffect(
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CSRData.at(CSR_TIME).physIndex);
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// U mode CSR
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r.ustatus = context->readMiscRegNoEffect(
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CSRData.at(CSR_USTATUS).physIndex) & CSRMasks.at(CSR_USTATUS);
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r.uie = context->readMiscReg(
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CSRData.at(CSR_UIE).physIndex) & CSRMasks.at(CSR_UIE);
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r.utvec = context->readMiscRegNoEffect(
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CSRData.at(CSR_UTVEC).physIndex);
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r.uscratch = context->readMiscRegNoEffect(
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CSRData.at(CSR_USCRATCH).physIndex);
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r.uepc = context->readMiscRegNoEffect(
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CSRData.at(CSR_UEPC).physIndex);
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r.ucause = context->readMiscRegNoEffect(
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CSRData.at(CSR_UCAUSE).physIndex);
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r.utval = context->readMiscRegNoEffect(
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CSRData.at(CSR_UTVAL).physIndex);
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r.uip = context->readMiscReg(
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CSRData.at(CSR_UIP).physIndex) & CSRMasks.at(CSR_UIP);
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// S mode CSR
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r.sstatus = context->readMiscRegNoEffect(
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CSRData.at(CSR_SSTATUS).physIndex) & CSRMasks.at(CSR_SSTATUS);
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r.sedeleg = context->readMiscRegNoEffect(
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CSRData.at(CSR_SEDELEG).physIndex);
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r.sideleg = context->readMiscRegNoEffect(
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CSRData.at(CSR_SIDELEG).physIndex);
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r.sie = context->readMiscReg(
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CSRData.at(CSR_SIE).physIndex) & CSRMasks.at(CSR_SIE);
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r.stvec = context->readMiscRegNoEffect(
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CSRData.at(CSR_STVEC).physIndex);
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r.scounteren = context->readMiscRegNoEffect(
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CSRData.at(CSR_SCOUNTEREN).physIndex);
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r.sscratch = context->readMiscRegNoEffect(
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CSRData.at(CSR_SSCRATCH).physIndex);
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r.sepc = context->readMiscRegNoEffect(
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CSRData.at(CSR_SEPC).physIndex);
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r.scause = context->readMiscRegNoEffect(
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CSRData.at(CSR_SCAUSE).physIndex);
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r.stval = context->readMiscRegNoEffect(
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CSRData.at(CSR_STVAL).physIndex);
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r.sip = context->readMiscReg(
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CSRData.at(CSR_SIP).physIndex) & CSRMasks.at(CSR_SIP);
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r.satp = context->readMiscRegNoEffect(
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CSRData.at(CSR_SATP).physIndex);
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// M mode CSR
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r.mvendorid = context->readMiscRegNoEffect(
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CSRData.at(CSR_MVENDORID).physIndex);
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r.marchid = context->readMiscRegNoEffect(
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CSRData.at(CSR_MARCHID).physIndex);
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r.mimpid = context->readMiscRegNoEffect(
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CSRData.at(CSR_MIMPID).physIndex);
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r.mhartid = context->readMiscRegNoEffect(
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CSRData.at(CSR_MHARTID).physIndex);
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r.mstatus = context->readMiscRegNoEffect(
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CSRData.at(CSR_MSTATUS).physIndex) & CSRMasks.at(CSR_MSTATUS);
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r.misa = context->readMiscRegNoEffect(
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CSRData.at(CSR_MISA).physIndex) & CSRMasks.at(CSR_MISA);
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r.medeleg = context->readMiscRegNoEffect(
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CSRData.at(CSR_MEDELEG).physIndex);
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r.mideleg = context->readMiscRegNoEffect(
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CSRData.at(CSR_MIDELEG).physIndex);
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r.mie = context->readMiscReg(
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CSRData.at(CSR_MIE).physIndex) & CSRMasks.at(CSR_MIE);
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r.mtvec = context->readMiscRegNoEffect(
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CSRData.at(CSR_MTVEC).physIndex);
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r.mcounteren = context->readMiscRegNoEffect(
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CSRData.at(CSR_MCOUNTEREN).physIndex);
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r.mscratch = context->readMiscRegNoEffect(
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CSRData.at(CSR_MSCRATCH).physIndex);
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r.mepc = context->readMiscRegNoEffect(
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CSRData.at(CSR_MEPC).physIndex);
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r.mcause = context->readMiscRegNoEffect(
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CSRData.at(CSR_MCAUSE).physIndex);
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r.mtval = context->readMiscRegNoEffect(
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CSRData.at(CSR_MTVAL).physIndex);
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r.mip = context->readMiscReg(
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CSRData.at(CSR_MIP).physIndex) & CSRMasks.at(CSR_MIP);
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// H mode CSR (to be implemented)
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}
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void
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RemoteGDB::RiscvGdbRegCache::setRegs(ThreadContext *context) const
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{
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// NOTE: no error will be reported for attempting to set masked bits.
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RegVal oldVal;
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int mask;
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RegVal newVal;
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DPRINTF(GDBAcc, "setregs in remotegdb \n");
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for (int i = 0; i < int_reg::NumArchRegs; i++)
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context->setReg(RegId(IntRegClass, i), r.gpr[i]);
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context->pcState(r.pc);
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// Floating point registers
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for (int i = 0; i < float_reg::NumRegs; i++)
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context->setReg(RegId(FloatRegClass, i), r.fpu[i]);
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oldVal = context->readMiscRegNoEffect(
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CSRData.at(CSR_FFLAGS).physIndex);
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mask = CSRMasks.at(CSR_FFLAGS);
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newVal = (oldVal & ~mask) | (r.fflags & mask);
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context->setMiscRegNoEffect(
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CSRData.at(CSR_FFLAGS).physIndex, newVal);
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oldVal = context->readMiscRegNoEffect(
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CSRData.at(CSR_FRM).physIndex);
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mask = CSRMasks.at(CSR_FRM);
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newVal = (oldVal & ~mask) | (r.frm & mask);
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context->setMiscRegNoEffect(
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CSRData.at(CSR_FRM).physIndex, newVal);
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oldVal = context->readMiscRegNoEffect(
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CSRData.at(CSR_FCSR).physIndex);
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mask = CSRMasks.at(CSR_FCSR);
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newVal = (oldVal & ~mask) | (r.fcsr & mask);
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context->setMiscRegNoEffect(
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CSRData.at(CSR_FCSR).physIndex, newVal);
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// CSR registers
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context->setMiscRegNoEffect(
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CSRData.at(CSR_CYCLE).physIndex, r.cycle);
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context->setMiscRegNoEffect(
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CSRData.at(CSR_TIME).physIndex, r.time);
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// U mode CSR
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oldVal = context->readMiscRegNoEffect(
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CSRData.at(CSR_USTATUS).physIndex);
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mask = CSRMasks.at(CSR_USTATUS);
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newVal = (oldVal & ~mask) | (r.ustatus & mask);
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context->setMiscRegNoEffect(
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CSRData.at(CSR_USTATUS).physIndex, newVal);
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oldVal = context->readMiscReg(
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CSRData.at(CSR_UIE).physIndex);
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mask = CSRMasks.at(CSR_UIE);
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newVal = (oldVal & ~mask) | (r.uie & mask);
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context->setMiscReg(
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CSRData.at(CSR_UIE).physIndex, newVal);
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context->setMiscRegNoEffect(
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CSRData.at(CSR_UTVEC).physIndex, r.utvec);
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context->setMiscRegNoEffect(
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CSRData.at(CSR_USCRATCH).physIndex, r.uscratch);
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context->setMiscRegNoEffect(
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CSRData.at(CSR_UEPC).physIndex, r.uepc);
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context->setMiscRegNoEffect(
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CSRData.at(CSR_UCAUSE).physIndex, r.ucause);
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context->setMiscRegNoEffect(
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CSRData.at(CSR_UTVAL).physIndex, r.utval);
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oldVal = context->readMiscReg(
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CSRData.at(CSR_UIP).physIndex);
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mask = CSRMasks.at(CSR_UIP);
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newVal = (oldVal & ~mask) | (r.uip & mask);
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context->setMiscReg(
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CSRData.at(CSR_UIP).physIndex, newVal);
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// S mode CSR
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oldVal = context->readMiscRegNoEffect(
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CSRData.at(CSR_SSTATUS).physIndex);
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mask = CSRMasks.at(CSR_SSTATUS);
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newVal = (oldVal & ~mask) | (r.sstatus & mask);
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context->setMiscRegNoEffect(
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CSRData.at(CSR_SSTATUS).physIndex, newVal);
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context->setMiscRegNoEffect(
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CSRData.at(CSR_SEDELEG).physIndex, r.sedeleg);
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context->setMiscRegNoEffect(
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CSRData.at(CSR_SIDELEG).physIndex, r.sideleg);
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oldVal = context->readMiscReg(
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CSRData.at(CSR_SIE).physIndex);
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mask = CSRMasks.at(CSR_SIE);
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newVal = (oldVal & ~mask) | (r.sie & mask);
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context->setMiscReg(
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CSRData.at(CSR_SIE).physIndex, newVal);
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context->setMiscRegNoEffect(
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CSRData.at(CSR_STVEC).physIndex, r.stvec);
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context->setMiscRegNoEffect(
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CSRData.at(CSR_SCOUNTEREN).physIndex, r.scounteren);
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context->setMiscRegNoEffect(
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CSRData.at(CSR_SSCRATCH).physIndex, r.sscratch);
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context->setMiscRegNoEffect(
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CSRData.at(CSR_SEPC).physIndex, r.sepc);
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context->setMiscRegNoEffect(
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CSRData.at(CSR_SCAUSE).physIndex, r.scause);
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context->setMiscRegNoEffect(
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CSRData.at(CSR_STVAL).physIndex, r.stval);
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oldVal = context->readMiscReg(
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CSRData.at(CSR_SIP).physIndex);
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mask = CSRMasks.at(CSR_SIP);
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newVal = (oldVal & ~mask) | (r.sip & mask);
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context->setMiscReg(
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CSRData.at(CSR_SIP).physIndex, newVal);
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context->setMiscRegNoEffect(
|
|
CSRData.at(CSR_SATP).physIndex, r.satp);
|
|
|
|
// M mode CSR
|
|
context->setMiscRegNoEffect(
|
|
CSRData.at(CSR_MVENDORID).physIndex, r.mvendorid);
|
|
context->setMiscRegNoEffect(
|
|
CSRData.at(CSR_MARCHID).physIndex, r.marchid);
|
|
context->setMiscRegNoEffect(
|
|
CSRData.at(CSR_MIMPID).physIndex, r.mimpid);
|
|
context->setMiscRegNoEffect(
|
|
CSRData.at(CSR_MHARTID).physIndex, r.mhartid);
|
|
oldVal = context->readMiscRegNoEffect(
|
|
CSRData.at(CSR_MSTATUS).physIndex);
|
|
mask = CSRMasks.at(CSR_MSTATUS);
|
|
newVal = (oldVal & ~mask) | (r.mstatus & mask);
|
|
context->setMiscRegNoEffect(
|
|
CSRData.at(CSR_MSTATUS).physIndex, newVal);
|
|
oldVal = context->readMiscRegNoEffect(
|
|
CSRData.at(CSR_MISA).physIndex);
|
|
mask = CSRMasks.at(CSR_MISA);
|
|
newVal = (oldVal & ~mask) | (r.misa & mask);
|
|
context->setMiscRegNoEffect(
|
|
CSRData.at(CSR_MISA).physIndex, newVal);
|
|
context->setMiscRegNoEffect(
|
|
CSRData.at(CSR_MEDELEG).physIndex, r.medeleg);
|
|
context->setMiscRegNoEffect(
|
|
CSRData.at(CSR_MIDELEG).physIndex, r.mideleg);
|
|
oldVal = context->readMiscReg(
|
|
CSRData.at(CSR_MIE).physIndex);
|
|
mask = CSRMasks.at(CSR_MIE);
|
|
newVal = (oldVal & ~mask) | (r.mie & mask);
|
|
context->setMiscReg(
|
|
CSRData.at(CSR_MIE).physIndex, newVal);
|
|
context->setMiscRegNoEffect(
|
|
CSRData.at(CSR_MTVEC).physIndex, r.mtvec);
|
|
context->setMiscRegNoEffect(
|
|
CSRData.at(CSR_MCOUNTEREN).physIndex, r.mcounteren);
|
|
context->setMiscRegNoEffect(
|
|
CSRData.at(CSR_MSCRATCH).physIndex, r.mscratch);
|
|
context->setMiscRegNoEffect(
|
|
CSRData.at(CSR_MEPC).physIndex, r.mepc);
|
|
context->setMiscRegNoEffect(
|
|
CSRData.at(CSR_MCAUSE).physIndex, r.mcause);
|
|
context->setMiscRegNoEffect(
|
|
CSRData.at(CSR_MTVAL).physIndex, r.mtval);
|
|
oldVal = context->readMiscReg(
|
|
CSRData.at(CSR_MIP).physIndex);
|
|
mask = CSRMasks.at(CSR_MIP);
|
|
newVal = (oldVal & ~mask) | (r.mip & mask);
|
|
context->setMiscReg(
|
|
CSRData.at(CSR_MIP).physIndex, newVal);
|
|
|
|
// H mode CSR (to be implemented)
|
|
}
|
|
|
|
bool
|
|
RemoteGDB::getXferFeaturesRead(const std::string &annex, std::string &output)
|
|
{
|
|
/**
|
|
* Blobs e.g. gdb_xml_riscv_target are generated by adding
|
|
* GdbXml(<xml_file_name>, <blob_name>) to src/arch/riscv/Sconscript.
|
|
*
|
|
* Import using #include blobs/<blob_name>.hh
|
|
*/
|
|
#define GDB_XML(x, s) \
|
|
{ \
|
|
x, std::string(reinterpret_cast<const char *>(Blobs::s), \
|
|
Blobs::s##_len) \
|
|
}
|
|
static const std::map<std::string, std::string> annexMap{
|
|
GDB_XML("target.xml", gdb_xml_riscv_target),
|
|
GDB_XML("riscv-64bit-cpu.xml", gdb_xml_riscv_cpu),
|
|
GDB_XML("riscv-64bit-fpu.xml", gdb_xml_riscv_fpu),
|
|
GDB_XML("riscv-64bit-csr.xml", gdb_xml_riscv_csr)};
|
|
#undef GDB_XML
|
|
auto it = annexMap.find(annex);
|
|
if (it == annexMap.end())
|
|
return false;
|
|
output = it->second;
|
|
return true;
|
|
}
|
|
|
|
BaseGdbRegCache *
|
|
RemoteGDB::gdbRegs()
|
|
{
|
|
return ®Cache;
|
|
}
|
|
|
|
} // namespace gem5
|