Jairo Balart 0473f8f65f cpu: Make the indirect predictor into a SimObject ...

Change-Id: Ice6549773def7d3e944fae450d4a079bc351e2ba
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/15319
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

2019-05-13 11:43:50 +00:00

..

arch

arch-arm: Add initial support for SVE contiguous loads/stores

2019-05-11 12:49:15 +00:00

base

dev-arm: Correct cast of template parameter

2019-04-01 15:55:58 +00:00

cpu

cpu: Make the indirect predictor into a SimObject

2019-05-13 11:43:50 +00:00

dev

dev: StreamID generation in DMA device

2019-05-03 08:38:12 +00:00

doc

mem: Minimize the use of MemObject.

2019-04-28 01:19:40 +00:00

doxygen

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gpu-compute

mem: Minimize the use of MemObject.

2019-04-28 01:19:40 +00:00

kern

arch: cpu: Track kernel stats using the base ISA agnostic type.

2019-04-30 03:49:40 +00:00

learning_gem5

learning_gem5: Fix vector port panic in SimpleCache

2019-04-08 22:51:38 +00:00

mem

mem-ruby: Replace string parameter in MultiBitSelBloomFilter

2019-05-12 17:22:01 +00:00

proto

cpu: Stop extracting inst_flags from the machInst.

2018-03-27 10:57:36 +00:00

python

mem: Minimize the use of MemObject.

2019-04-28 01:19:40 +00:00

sim

sim-se: correct statfs inclusion on !linux host

2019-05-06 18:20:44 +00:00

systemc

systemc: Add a distinct async_request_update mechanism.

2019-04-30 01:27:45 +00:00

unittest

python: Replace dict.has_key with 'key in dict'

2019-02-12 17:36:12 +00:00

Doxyfile

misc: Fix BaseCPU doxygen

2018-07-10 16:41:40 +00:00

SConscript

scons: fix disable_partial logic for fast binary

2019-03-18 22:22:25 +00:00