d11c40dcac
This ensures `isort` is applied to all files in the repo. Change-Id: Ib7ced1c924ef1639542bf0d1a01c5737f6ba43e9
113 lines
4.1 KiB
Python
113 lines
4.1 KiB
Python
# Copyright (c) 2021 The Regents of the University of California
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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"""
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This script is used for running a traffic generator connected to a memory
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device. It supports linear and random accesses with a configurable amount
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of write traffic.
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By default, this scripts runs with one channel (two pseudo channels) of HBM2
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and this channel is driven with 32GiB/s of traffic for 1ms.
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"""
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import argparse
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from m5.objects import MemorySize
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from gem5.components.boards.test_board import TestBoard
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from gem5.components.memory.dram_interfaces.hbm import HBM_2000_4H_1x64
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from gem5.components.memory.hbm import HighBandwidthMemory
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from gem5.components.processors.linear_generator import LinearGenerator
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from gem5.components.processors.random_generator import RandomGenerator
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from gem5.simulate.simulator import Simulator
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def generator_factory(
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generator_class: str, rd_perc: int, mem_size: MemorySize
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):
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rd_perc = int(rd_perc)
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if rd_perc > 100 or rd_perc < 0:
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raise ValueError(
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"Read percentage has to be an integer number between 0 and 100."
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)
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if generator_class == "LinearGenerator":
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return LinearGenerator(
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duration="1ms", rate="32GiB/s", max_addr=mem_size, rd_perc=rd_perc
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)
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elif generator_class == "RandomGenerator":
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return RandomGenerator(
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duration="1ms", rate="32GiB/s", max_addr=mem_size, rd_perc=rd_perc
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)
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else:
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raise ValueError(f"Unknown generator class {generator_class}")
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parser = argparse.ArgumentParser(
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description="A traffic generator that can be used to test a gem5 "
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"memory component."
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)
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parser.add_argument(
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"generator_class",
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type=str,
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help="The class of generator to use.",
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choices=[
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"LinearGenerator",
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"RandomGenerator",
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],
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)
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parser.add_argument(
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"read_percentage",
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type=int,
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help="Percentage of read requests in the generated traffic.",
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)
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args = parser.parse_args()
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# Single pair of HBM2 pseudo channels. This can be replaced with any
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# single ported memory device
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memory = HighBandwidthMemory(HBM_2000_4H_1x64, 1, 128)
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generator = generator_factory(
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args.generator_class, args.read_percentage, memory.get_size()
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)
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# We use the Test Board. This is a special board to run traffic generation
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# tasks. Can replace the cache_hierarchy with any hierarchy to simulate the
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# cache as well as the memory
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board = TestBoard(
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clk_freq="1GHz", # Ignored for these generators
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generator=generator, # We pass the traffic generator as the processor.
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memory=memory,
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# With no cache hierarchy the test board will directly connect the
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# generator to the memory
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cache_hierarchy=None,
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)
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simulator = Simulator(board=board)
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simulator.run()
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