dff879cf21
Previously the scalar cache path used the same latency parameter as the vector cache path for memory requests. This commit adds new parameters for the scalar cache path latencies. This commit also modifies the model to use the new latency parameter to set the memory request latency in the scalar cache. The new paramters are '--scalar-mem-req-latency' and '--scalar-mem-resp-latency' and are set to default values of 50 and 0 respectively Change-Id: I7483f780f2fc0cfbc320ed1fd0c2ee3e2dfc7af2 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65511 Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com> Maintainer: Jason Lowe-Power <power.jg@gmail.com> Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
1148 lines
37 KiB
C++
1148 lines
37 KiB
C++
/*
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* Copyright (c) 2011-2015 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __COMPUTE_UNIT_HH__
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#define __COMPUTE_UNIT_HH__
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#include <deque>
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#include <map>
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#include <unordered_set>
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#include <vector>
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#include "base/callback.hh"
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#include "base/compiler.hh"
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#include "base/statistics.hh"
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#include "base/stats/group.hh"
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#include "base/types.hh"
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#include "config/the_gpu_isa.hh"
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#include "enums/PrefetchType.hh"
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#include "gpu-compute/comm.hh"
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#include "gpu-compute/exec_stage.hh"
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#include "gpu-compute/fetch_stage.hh"
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#include "gpu-compute/global_memory_pipeline.hh"
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#include "gpu-compute/hsa_queue_entry.hh"
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#include "gpu-compute/local_memory_pipeline.hh"
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#include "gpu-compute/register_manager.hh"
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#include "gpu-compute/scalar_memory_pipeline.hh"
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#include "gpu-compute/schedule_stage.hh"
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#include "gpu-compute/scoreboard_check_stage.hh"
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#include "mem/port.hh"
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#include "mem/token_port.hh"
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#include "sim/clocked_object.hh"
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namespace gem5
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{
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class HSAQueueEntry;
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class LdsChunk;
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class ScalarRegisterFile;
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class Shader;
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class VectorRegisterFile;
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struct ComputeUnitParams;
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enum EXEC_POLICY
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{
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OLDEST = 0,
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RR
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};
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enum TLB_CACHE
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{
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TLB_MISS_CACHE_MISS = 0,
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TLB_MISS_CACHE_HIT,
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TLB_HIT_CACHE_MISS,
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TLB_HIT_CACHE_HIT
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};
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/**
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* WF barrier slots. This represents the barrier resource for
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* WF-level barriers (i.e., barriers to sync WFs within a WG).
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*/
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class WFBarrier
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{
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public:
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WFBarrier() : _numAtBarrier(0), _maxBarrierCnt(0)
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{
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}
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static const int InvalidID = -1;
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int
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numAtBarrier() const
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{
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return _numAtBarrier;
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}
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/**
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* Number of WFs that have not yet reached the barrier.
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*/
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int
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numYetToReachBarrier() const
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{
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return _maxBarrierCnt - _numAtBarrier;
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}
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int
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maxBarrierCnt() const
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{
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return _maxBarrierCnt;
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}
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/**
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* Set the maximum barrier count (i.e., the number of WFs that are
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* participating in the barrier).
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*/
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void
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setMaxBarrierCnt(int max_barrier_cnt)
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{
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_maxBarrierCnt = max_barrier_cnt;
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}
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/**
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* Mark that a WF has reached the barrier.
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*/
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void
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incNumAtBarrier()
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{
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assert(_numAtBarrier < _maxBarrierCnt);
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++_numAtBarrier;
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}
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/**
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* Have all WFs participating in this barrier reached the barrier?
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* If so, then the barrier is satisfied and WFs may proceed past
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* the barrier.
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*/
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bool
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allAtBarrier() const
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{
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return _numAtBarrier == _maxBarrierCnt;
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}
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/**
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* Decrement the number of WFs that are participating in this barrier.
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* This should be called when a WF exits.
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*/
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void
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decMaxBarrierCnt()
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{
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assert(_maxBarrierCnt > 0);
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--_maxBarrierCnt;
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}
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/**
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* Release this barrier resource so it can be used by other WGs. This
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* is generally called when a WG has finished.
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*/
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void
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release()
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{
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_numAtBarrier = 0;
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_maxBarrierCnt = 0;
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}
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/**
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* Reset the barrier. This is used to reset the barrier, usually when
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* a dynamic instance of a barrier has been satisfied.
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*/
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void
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reset()
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{
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_numAtBarrier = 0;
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}
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private:
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/**
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* The number of WFs in the WG that have reached the barrier. Once
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* the number of WFs that reach a barrier matches the number of WFs
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* in the WG, the barrier is satisfied.
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*/
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int _numAtBarrier;
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/**
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* The maximum number of WFs that can reach this barrier. This is
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* essentially the number of WFs in the WG, and a barrier is satisfied
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* when the number of WFs that reach the barrier equal this value. If
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* a WF exits early it must decrement this value so that it is no
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* longer considered for this barrier.
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*/
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int _maxBarrierCnt;
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};
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class ComputeUnit : public ClockedObject
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{
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public:
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// Execution resources
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//
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// The ordering of units is:
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// Vector ALUs
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// Scalar ALUs
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// GM Pipe
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// LM Pipe
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// Scalar Mem Pipe
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//
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// Note: the ordering of units is important and the code assumes the
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// above ordering. However, there may be more than one resource of
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// each type (e.g., 4 VALUs or 2 SALUs)
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int numVectorGlobalMemUnits;
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// Resource control for global memory to VRF data/address bus
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WaitClass glbMemToVrfBus;
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// Resource control for Vector Register File->Global Memory pipe buses
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WaitClass vrfToGlobalMemPipeBus;
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// Resource control for Vector Global Memory execution unit
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WaitClass vectorGlobalMemUnit;
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int numVectorSharedMemUnits;
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// Resource control for local memory to VRF data/address bus
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WaitClass locMemToVrfBus;
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// Resource control for Vector Register File->Local Memory pipe buses
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WaitClass vrfToLocalMemPipeBus;
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// Resource control for Vector Shared/Local Memory execution unit
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WaitClass vectorSharedMemUnit;
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int numScalarMemUnits;
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// Resource control for scalar memory to SRF data/address bus
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WaitClass scalarMemToSrfBus;
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// Resource control for Scalar Register File->Scalar Memory pipe buses
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WaitClass srfToScalarMemPipeBus;
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// Resource control for Scalar Memory execution unit
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WaitClass scalarMemUnit;
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// vector ALU execution resources
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int numVectorALUs;
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std::vector<WaitClass> vectorALUs;
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// scalar ALU execution resources
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int numScalarALUs;
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std::vector<WaitClass> scalarALUs;
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// Return total number of execution units on this CU
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int numExeUnits() const;
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// index into readyList of the first memory unit
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int firstMemUnit() const;
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// index into readyList of the last memory unit
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int lastMemUnit() const;
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// index into scalarALUs vector of SALU used by the wavefront
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int mapWaveToScalarAlu(Wavefront *w) const;
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// index into readyList of SALU used by wavefront
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int mapWaveToScalarAluGlobalIdx(Wavefront *w) const;
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// index into readyList of Global Memory unit used by wavefront
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int mapWaveToGlobalMem(Wavefront *w) const;
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// index into readyList of Local Memory unit used by wavefront
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int mapWaveToLocalMem(Wavefront *w) const;
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// index into readyList of Scalar Memory unit used by wavefront
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int mapWaveToScalarMem(Wavefront *w) const;
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int vrfToCoalescerBusWidth; // VRF->Coalescer data bus width in bytes
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int coalescerToVrfBusWidth; // Coalescer->VRF data bus width in bytes
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int numCyclesPerStoreTransfer; // number of cycles per vector store
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int numCyclesPerLoadTransfer; // number of cycles per vector load
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// track presence of dynamic instructions in the Schedule pipeline
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// stage. This is used to check the readiness of the oldest,
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// non-dispatched instruction of every WF in the Scoreboard stage.
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std::unordered_set<uint64_t> pipeMap;
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RegisterManager* registerManager;
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FetchStage fetchStage;
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ScoreboardCheckStage scoreboardCheckStage;
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ScheduleStage scheduleStage;
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ExecStage execStage;
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GlobalMemPipeline globalMemoryPipe;
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LocalMemPipeline localMemoryPipe;
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ScalarMemPipeline scalarMemoryPipe;
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EventFunctionWrapper tickEvent;
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typedef ComputeUnitParams Params;
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std::vector<std::vector<Wavefront*>> wfList;
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int cu_id;
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// array of vector register files, one per SIMD
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std::vector<VectorRegisterFile*> vrf;
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// array of scalar register files, one per SIMD
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std::vector<ScalarRegisterFile*> srf;
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// Width per VALU/SIMD unit: number of work items that can be executed
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// on the vector ALU simultaneously in a SIMD unit
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int simdWidth;
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// number of pipe stages for bypassing data to next dependent single
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// precision vector instruction inside the vector ALU pipeline
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int spBypassPipeLength;
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// number of pipe stages for bypassing data to next dependent double
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// precision vector instruction inside the vector ALU pipeline
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int dpBypassPipeLength;
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// number of pipe stages for scalar ALU
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int scalarPipeStages;
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// number of pipe stages for operand collection & distribution network
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int operandNetworkLength;
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// number of cycles per instruction issue period
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Cycles issuePeriod;
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// VRF to GM Bus latency
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Cycles vrf_gm_bus_latency;
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// SRF to Scalar Mem Bus latency
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Cycles srf_scm_bus_latency;
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// VRF to LM Bus latency
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Cycles vrf_lm_bus_latency;
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// tracks the last cycle a vector instruction was executed on a SIMD
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std::vector<uint64_t> lastExecCycle;
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// tracks the number of dyn inst executed per SIMD
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std::vector<uint64_t> instExecPerSimd;
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// true if we allow a separate TLB per lane
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bool perLaneTLB;
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// if 0, TLB prefetching is off.
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int prefetchDepth;
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// if fixed-stride prefetching, this is the stride.
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int prefetchStride;
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std::vector<Addr> lastVaddrCU;
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std::vector<std::vector<Addr>> lastVaddrSimd;
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std::vector<std::vector<std::vector<Addr>>> lastVaddrWF;
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enums::PrefetchType prefetchType;
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EXEC_POLICY exec_policy;
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bool debugSegFault;
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// Idle CU timeout in ticks
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Tick idleCUTimeout;
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int idleWfs;
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bool functionalTLB;
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bool localMemBarrier;
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/*
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* for Counting page accesses
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*/
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bool countPages;
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Shader *shader;
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Tick req_tick_latency;
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Tick resp_tick_latency;
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Tick scalar_req_tick_latency;
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Tick scalar_resp_tick_latency;
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/**
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* Number of WFs to schedule to each SIMD. This vector is populated
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* by hasDispResources(), and consumed by the subsequent call to
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* dispWorkgroup(), to schedule the specified number of WFs to the
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* SIMD units. Entry I provides the number of WFs to schedule to SIMD I.
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*/
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std::vector<int> numWfsToSched;
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// number of currently reserved vector registers per SIMD unit
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std::vector<int> vectorRegsReserved;
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// number of currently reserved scalar registers per SIMD unit
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std::vector<int> scalarRegsReserved;
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// number of vector registers per SIMD unit
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int numVecRegsPerSimd;
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// number of available scalar registers per SIMD unit
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int numScalarRegsPerSimd;
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// this hash map will keep track of page divergence
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// per memory instruction per wavefront. The hash map
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// is cleared in GPUDynInst::updateStats() in gpu_dyn_inst.cc.
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std::map<Addr, int> pagesTouched;
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void insertInPipeMap(Wavefront *w);
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void deleteFromPipeMap(Wavefront *w);
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ComputeUnit(const Params &p);
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~ComputeUnit();
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// Timing Functions
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int oprNetPipeLength() const { return operandNetworkLength; }
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int simdUnitWidth() const { return simdWidth; }
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int spBypassLength() const { return spBypassPipeLength; }
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int dpBypassLength() const { return dpBypassPipeLength; }
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int scalarPipeLength() const { return scalarPipeStages; }
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int storeBusLength() const { return numCyclesPerStoreTransfer; }
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int loadBusLength() const { return numCyclesPerLoadTransfer; }
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int wfSize() const { return wavefrontSize; }
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void exec();
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void initiateFetch(Wavefront *wavefront);
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void fetch(PacketPtr pkt, Wavefront *wavefront);
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void fillKernelState(Wavefront *w, HSAQueueEntry *task);
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void startWavefront(Wavefront *w, int waveId, LdsChunk *ldsChunk,
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HSAQueueEntry *task, int bar_id,
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bool fetchContext=false);
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void doInvalidate(RequestPtr req, int kernId);
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void doFlush(GPUDynInstPtr gpuDynInst);
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void dispWorkgroup(HSAQueueEntry *task, int num_wfs_in_wg);
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bool hasDispResources(HSAQueueEntry *task, int &num_wfs_in_wg);
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int cacheLineSize() const { return _cacheLineSize; }
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int getCacheLineBits() const { return cacheLineBits; }
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void resetRegisterPool();
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private:
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WFBarrier&
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barrierSlot(int bar_id)
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{
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assert(bar_id > WFBarrier::InvalidID);
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return wfBarrierSlots.at(bar_id);
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}
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int
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getFreeBarrierId()
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{
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assert(freeBarrierIds.size());
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auto free_bar_id = freeBarrierIds.begin();
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int bar_id = *free_bar_id;
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freeBarrierIds.erase(free_bar_id);
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return bar_id;
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}
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public:
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int numYetToReachBarrier(int bar_id);
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bool allAtBarrier(int bar_id);
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void incNumAtBarrier(int bar_id);
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int numAtBarrier(int bar_id);
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int maxBarrierCnt(int bar_id);
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void resetBarrier(int bar_id);
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void decMaxBarrierCnt(int bar_id);
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void releaseBarrier(int bar_id);
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void releaseWFsFromBarrier(int bar_id);
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int numBarrierSlots() const { return _numBarrierSlots; }
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template<typename c0, typename c1>
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void doSmReturn(GPUDynInstPtr gpuDynInst);
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virtual void init() override;
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void sendRequest(GPUDynInstPtr gpuDynInst, PortID index, PacketPtr pkt);
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void sendScalarRequest(GPUDynInstPtr gpuDynInst, PacketPtr pkt);
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void injectGlobalMemFence(GPUDynInstPtr gpuDynInst,
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bool kernelMemSync,
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RequestPtr req=nullptr);
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void handleMemPacket(PacketPtr pkt, int memport_index);
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bool processTimingPacket(PacketPtr pkt);
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void processFetchReturn(PacketPtr pkt);
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void updatePageDivergenceDist(Addr addr);
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RequestorID requestorId() { return _requestorId; }
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RequestorID vramRequestorId();
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bool isDone() const;
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bool isVectorAluIdle(uint32_t simdId) const;
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void handleSQCReturn(PacketPtr pkt);
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protected:
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RequestorID _requestorId;
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LdsState &lds;
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public:
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LdsState &
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getLds() const
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{
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return lds;
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}
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int32_t
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getRefCounter(const uint32_t dispatchId, const uint32_t wgId) const;
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[[nodiscard]] bool sendToLds(GPUDynInstPtr gpuDynInst);
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typedef std::unordered_map<Addr, std::pair<int, int>> pageDataStruct;
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pageDataStruct pageAccesses;
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|
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void exitCallback();
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|
|
class GMTokenPort : public TokenRequestPort
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|
{
|
|
public:
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|
GMTokenPort(const std::string& name, SimObject *owner,
|
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PortID id = InvalidPortID)
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: TokenRequestPort(name, owner, id)
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{ }
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~GMTokenPort() { }
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protected:
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bool recvTimingResp(PacketPtr) { return false; }
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void recvReqRetry() { }
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};
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// Manager for the number of tokens available to this compute unit to
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// send global memory request packets to the coalescer this is only used
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// between global memory pipe and TCP coalescer.
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TokenManager *memPortTokens;
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GMTokenPort gmTokenPort;
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|
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/** Data access Port **/
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|
class DataPort : public RequestPort
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{
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|
public:
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DataPort(const std::string &_name, ComputeUnit *_cu, PortID id)
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: RequestPort(_name, _cu, id), computeUnit(_cu) { }
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|
|
bool snoopRangeSent;
|
|
|
|
struct SenderState : public Packet::SenderState
|
|
{
|
|
GPUDynInstPtr _gpuDynInst;
|
|
PortID port_index;
|
|
Packet::SenderState *saved;
|
|
|
|
SenderState(GPUDynInstPtr gpuDynInst, PortID _port_index,
|
|
Packet::SenderState *sender_state=nullptr)
|
|
: _gpuDynInst(gpuDynInst),
|
|
port_index(_port_index),
|
|
saved(sender_state) { }
|
|
};
|
|
|
|
class SystemHubEvent : public Event
|
|
{
|
|
DataPort *dataPort;
|
|
PacketPtr reqPkt;
|
|
|
|
public:
|
|
SystemHubEvent(PacketPtr pkt, DataPort *_dataPort)
|
|
: dataPort(_dataPort), reqPkt(pkt)
|
|
{
|
|
setFlags(Event::AutoDelete);
|
|
}
|
|
|
|
void
|
|
process()
|
|
{
|
|
// DMAs do not operate on packets and therefore do not
|
|
// convert to a response. Do that here instead.
|
|
reqPkt->makeResponse();
|
|
dataPort->handleResponse(reqPkt);
|
|
}
|
|
};
|
|
|
|
void processMemReqEvent(PacketPtr pkt);
|
|
EventFunctionWrapper *createMemReqEvent(PacketPtr pkt);
|
|
|
|
void processMemRespEvent(PacketPtr pkt);
|
|
EventFunctionWrapper *createMemRespEvent(PacketPtr pkt);
|
|
|
|
std::deque<std::pair<PacketPtr, GPUDynInstPtr>> retries;
|
|
|
|
bool handleResponse(PacketPtr pkt);
|
|
|
|
protected:
|
|
ComputeUnit *computeUnit;
|
|
|
|
virtual bool recvTimingResp(PacketPtr pkt);
|
|
virtual Tick recvAtomic(PacketPtr pkt) { return 0; }
|
|
virtual void recvFunctional(PacketPtr pkt) { }
|
|
virtual void recvRangeChange() { }
|
|
virtual void recvReqRetry();
|
|
|
|
virtual void
|
|
getDeviceAddressRanges(AddrRangeList &resp, bool &snoop)
|
|
{
|
|
resp.clear();
|
|
snoop = true;
|
|
}
|
|
|
|
};
|
|
|
|
// Scalar data cache access port
|
|
class ScalarDataPort : public RequestPort
|
|
{
|
|
public:
|
|
ScalarDataPort(const std::string &_name, ComputeUnit *_cu)
|
|
: RequestPort(_name, _cu), computeUnit(_cu)
|
|
{
|
|
}
|
|
|
|
bool recvTimingResp(PacketPtr pkt) override;
|
|
void recvReqRetry() override;
|
|
|
|
struct SenderState : public Packet::SenderState
|
|
{
|
|
SenderState(GPUDynInstPtr gpuDynInst,
|
|
Packet::SenderState *sender_state=nullptr)
|
|
: _gpuDynInst(gpuDynInst), saved(sender_state)
|
|
{
|
|
}
|
|
|
|
GPUDynInstPtr _gpuDynInst;
|
|
Packet::SenderState *saved;
|
|
};
|
|
|
|
class MemReqEvent : public Event
|
|
{
|
|
private:
|
|
ScalarDataPort &scalarDataPort;
|
|
PacketPtr pkt;
|
|
|
|
public:
|
|
MemReqEvent(ScalarDataPort &_scalar_data_port, PacketPtr _pkt)
|
|
: Event(), scalarDataPort(_scalar_data_port), pkt(_pkt)
|
|
{
|
|
setFlags(Event::AutoDelete);
|
|
}
|
|
|
|
void process();
|
|
const char *description() const;
|
|
};
|
|
|
|
class SystemHubEvent : public Event
|
|
{
|
|
ScalarDataPort *dataPort;
|
|
PacketPtr reqPkt;
|
|
|
|
public:
|
|
SystemHubEvent(PacketPtr pkt, ScalarDataPort *_dataPort)
|
|
: dataPort(_dataPort), reqPkt(pkt)
|
|
{
|
|
setFlags(Event::AutoDelete);
|
|
}
|
|
|
|
void
|
|
process()
|
|
{
|
|
// DMAs do not operate on packets and therefore do not
|
|
// convert to a response. Do that here instead.
|
|
reqPkt->makeResponse();
|
|
dataPort->handleResponse(reqPkt);
|
|
}
|
|
};
|
|
|
|
bool handleResponse(PacketPtr pkt);
|
|
|
|
std::deque<PacketPtr> retries;
|
|
|
|
private:
|
|
ComputeUnit *computeUnit;
|
|
};
|
|
|
|
// Instruction cache access port
|
|
class SQCPort : public RequestPort
|
|
{
|
|
public:
|
|
SQCPort(const std::string &_name, ComputeUnit *_cu)
|
|
: RequestPort(_name, _cu), computeUnit(_cu) { }
|
|
|
|
bool snoopRangeSent;
|
|
|
|
struct SenderState : public Packet::SenderState
|
|
{
|
|
Wavefront *wavefront;
|
|
Packet::SenderState *saved;
|
|
// kernel id to be used in handling I-Cache invalidate response
|
|
int kernId;
|
|
|
|
SenderState(Wavefront *_wavefront, Packet::SenderState
|
|
*sender_state=nullptr, int _kernId=-1)
|
|
: wavefront(_wavefront), saved(sender_state),
|
|
kernId(_kernId){ }
|
|
};
|
|
|
|
std::deque<std::pair<PacketPtr, Wavefront*>> retries;
|
|
|
|
protected:
|
|
ComputeUnit *computeUnit;
|
|
|
|
virtual bool recvTimingResp(PacketPtr pkt);
|
|
virtual Tick recvAtomic(PacketPtr pkt) { return 0; }
|
|
virtual void recvFunctional(PacketPtr pkt) { }
|
|
virtual void recvRangeChange() { }
|
|
virtual void recvReqRetry();
|
|
|
|
virtual void
|
|
getDeviceAddressRanges(AddrRangeList &resp, bool &snoop)
|
|
{
|
|
resp.clear();
|
|
snoop = true;
|
|
}
|
|
};
|
|
|
|
/** Data TLB port **/
|
|
class DTLBPort : public RequestPort
|
|
{
|
|
public:
|
|
DTLBPort(const std::string &_name, ComputeUnit *_cu, PortID id)
|
|
: RequestPort(_name, _cu, id), computeUnit(_cu),
|
|
stalled(false)
|
|
{ }
|
|
|
|
bool isStalled() { return stalled; }
|
|
void stallPort() { stalled = true; }
|
|
void unstallPort() { stalled = false; }
|
|
|
|
/**
|
|
* here we queue all the translation requests that were
|
|
* not successfully sent.
|
|
*/
|
|
std::deque<PacketPtr> retries;
|
|
|
|
/** SenderState is information carried along with the packet
|
|
* throughout the TLB hierarchy
|
|
*/
|
|
struct SenderState: public Packet::SenderState
|
|
{
|
|
// the memInst that this is associated with
|
|
GPUDynInstPtr _gpuDynInst;
|
|
|
|
// the lane in the memInst this is associated with, so we send
|
|
// the memory request down the right port
|
|
PortID portIndex;
|
|
|
|
// constructor used for packets involved in timing accesses
|
|
SenderState(GPUDynInstPtr gpuDynInst, PortID port_index)
|
|
: _gpuDynInst(gpuDynInst), portIndex(port_index) { }
|
|
|
|
};
|
|
|
|
protected:
|
|
ComputeUnit *computeUnit;
|
|
bool stalled;
|
|
|
|
virtual bool recvTimingResp(PacketPtr pkt);
|
|
virtual Tick recvAtomic(PacketPtr pkt) { return 0; }
|
|
virtual void recvFunctional(PacketPtr pkt) { }
|
|
virtual void recvRangeChange() { }
|
|
virtual void recvReqRetry();
|
|
};
|
|
|
|
class ScalarDTLBPort : public RequestPort
|
|
{
|
|
public:
|
|
ScalarDTLBPort(const std::string &_name, ComputeUnit *_cu)
|
|
: RequestPort(_name, _cu), computeUnit(_cu), stalled(false)
|
|
{
|
|
}
|
|
|
|
struct SenderState : public Packet::SenderState
|
|
{
|
|
SenderState(GPUDynInstPtr gpuDynInst) : _gpuDynInst(gpuDynInst) { }
|
|
GPUDynInstPtr _gpuDynInst;
|
|
};
|
|
|
|
bool recvTimingResp(PacketPtr pkt) override;
|
|
void recvReqRetry() override { assert(false); }
|
|
|
|
bool isStalled() const { return stalled; }
|
|
void stallPort() { stalled = true; }
|
|
void unstallPort() { stalled = false; }
|
|
|
|
std::deque<PacketPtr> retries;
|
|
|
|
private:
|
|
ComputeUnit *computeUnit;
|
|
bool stalled;
|
|
};
|
|
|
|
class ITLBPort : public RequestPort
|
|
{
|
|
public:
|
|
ITLBPort(const std::string &_name, ComputeUnit *_cu)
|
|
: RequestPort(_name, _cu), computeUnit(_cu), stalled(false) { }
|
|
|
|
|
|
bool isStalled() { return stalled; }
|
|
void stallPort() { stalled = true; }
|
|
void unstallPort() { stalled = false; }
|
|
|
|
/**
|
|
* here we queue all the translation requests that were
|
|
* not successfully sent.
|
|
*/
|
|
std::deque<PacketPtr> retries;
|
|
|
|
/** SenderState is information carried along with the packet
|
|
* throughout the TLB hierarchy
|
|
*/
|
|
struct SenderState: public Packet::SenderState
|
|
{
|
|
// The wavefront associated with this request
|
|
Wavefront *wavefront;
|
|
|
|
SenderState(Wavefront *_wavefront) : wavefront(_wavefront) { }
|
|
};
|
|
|
|
protected:
|
|
ComputeUnit *computeUnit;
|
|
bool stalled;
|
|
|
|
virtual bool recvTimingResp(PacketPtr pkt);
|
|
virtual Tick recvAtomic(PacketPtr pkt) { return 0; }
|
|
virtual void recvFunctional(PacketPtr pkt) { }
|
|
virtual void recvRangeChange() { }
|
|
virtual void recvReqRetry();
|
|
};
|
|
|
|
/**
|
|
* the port intended to communicate between the CU and its LDS
|
|
*/
|
|
class LDSPort : public RequestPort
|
|
{
|
|
public:
|
|
LDSPort(const std::string &_name, ComputeUnit *_cu)
|
|
: RequestPort(_name, _cu), computeUnit(_cu)
|
|
{
|
|
}
|
|
|
|
bool isStalled() const { return stalled; }
|
|
void stallPort() { stalled = true; }
|
|
void unstallPort() { stalled = false; }
|
|
|
|
/**
|
|
* here we queue all the requests that were
|
|
* not successfully sent.
|
|
*/
|
|
std::queue<PacketPtr> retries;
|
|
|
|
/**
|
|
* SenderState is information carried along with the packet, esp. the
|
|
* GPUDynInstPtr
|
|
*/
|
|
class SenderState: public Packet::SenderState
|
|
{
|
|
protected:
|
|
// The actual read/write/atomic request that goes with this command
|
|
GPUDynInstPtr _gpuDynInst = nullptr;
|
|
|
|
public:
|
|
SenderState(GPUDynInstPtr gpuDynInst):
|
|
_gpuDynInst(gpuDynInst)
|
|
{
|
|
}
|
|
|
|
GPUDynInstPtr
|
|
getMemInst() const
|
|
{
|
|
return _gpuDynInst;
|
|
}
|
|
};
|
|
|
|
virtual bool
|
|
sendTimingReq(PacketPtr pkt);
|
|
|
|
protected:
|
|
|
|
bool stalled = false; ///< whether or not it is stalled
|
|
|
|
ComputeUnit *computeUnit;
|
|
|
|
virtual bool
|
|
recvTimingResp(PacketPtr pkt);
|
|
|
|
virtual Tick
|
|
recvAtomic(PacketPtr pkt) { return 0; }
|
|
|
|
virtual void
|
|
recvFunctional(PacketPtr pkt)
|
|
{
|
|
}
|
|
|
|
virtual void
|
|
recvRangeChange()
|
|
{
|
|
}
|
|
|
|
virtual void
|
|
recvReqRetry();
|
|
};
|
|
|
|
/** The port to access the Local Data Store
|
|
* Can be connected to a LDS object
|
|
*/
|
|
LDSPort ldsPort;
|
|
|
|
TokenManager *
|
|
getTokenManager()
|
|
{
|
|
return memPortTokens;
|
|
}
|
|
|
|
/** The memory port for SIMD data accesses.
|
|
* Can be connected to PhysMem for Ruby for timing simulations
|
|
*/
|
|
std::vector<DataPort> memPort;
|
|
// port to the TLB hierarchy (i.e., the L1 TLB)
|
|
std::vector<DTLBPort> tlbPort;
|
|
// port to the scalar data cache
|
|
ScalarDataPort scalarDataPort;
|
|
// port to the scalar data TLB
|
|
ScalarDTLBPort scalarDTLBPort;
|
|
// port to the SQC (i.e. the I-cache)
|
|
SQCPort sqcPort;
|
|
// port to the SQC TLB (there's a separate TLB for each I-cache)
|
|
ITLBPort sqcTLBPort;
|
|
|
|
Port &
|
|
getPort(const std::string &if_name, PortID idx) override
|
|
{
|
|
if (if_name == "memory_port" && idx < memPort.size()) {
|
|
return memPort[idx];
|
|
} else if (if_name == "translation_port" && idx < tlbPort.size()) {
|
|
return tlbPort[idx];
|
|
} else if (if_name == "scalar_port") {
|
|
return scalarDataPort;
|
|
} else if (if_name == "scalar_tlb_port") {
|
|
return scalarDTLBPort;
|
|
} else if (if_name == "sqc_port") {
|
|
return sqcPort;
|
|
} else if (if_name == "sqc_tlb_port") {
|
|
return sqcTLBPort;
|
|
} else if (if_name == "ldsPort") {
|
|
return ldsPort;
|
|
} else if (if_name == "gmTokenPort") {
|
|
return gmTokenPort;
|
|
} else {
|
|
return ClockedObject::getPort(if_name, idx);
|
|
}
|
|
}
|
|
|
|
InstSeqNum getAndIncSeqNum() { return globalSeqNum++; }
|
|
|
|
private:
|
|
const int _cacheLineSize;
|
|
const int _numBarrierSlots;
|
|
int cacheLineBits;
|
|
InstSeqNum globalSeqNum;
|
|
int wavefrontSize;
|
|
|
|
/**
|
|
* TODO: Update these comments once the pipe stage interface has
|
|
* been fully refactored.
|
|
*
|
|
* Pipeline stage interfaces.
|
|
*
|
|
* Buffers used to communicate between various pipeline stages
|
|
* List of waves which will be dispatched to
|
|
* each execution resource. An EXREADY implies
|
|
* dispatch list is non-empty and
|
|
* execution unit has something to execute
|
|
* this cycle. Currently, the dispatch list of
|
|
* an execution resource can hold only one wave because
|
|
* an execution resource can execute only one wave in a cycle.
|
|
* dispatchList is used to communicate between schedule
|
|
* and exec stage
|
|
*
|
|
* At a high level, the following intra-/inter-stage communication occurs:
|
|
* SCB to SCH: readyList provides per exec resource list of waves that
|
|
* passed dependency and readiness checks. If selected by
|
|
* scheduler, attempt to add wave to schList conditional on
|
|
* RF support.
|
|
* SCH: schList holds waves that are gathering operands or waiting
|
|
* for execution resource availability. Once ready, waves are
|
|
* placed on the dispatchList as candidates for execution. A wave
|
|
* may spend multiple cycles in SCH stage, on the schList due to
|
|
* RF access conflicts or execution resource contention.
|
|
* SCH to EX: dispatchList holds waves that are ready to be executed.
|
|
* LM/FLAT arbitration may remove an LM wave and place it
|
|
* back on the schList. RF model may also force a wave back
|
|
* to the schList if using the detailed model.
|
|
*/
|
|
ScoreboardCheckToSchedule scoreboardCheckToSchedule;
|
|
ScheduleToExecute scheduleToExecute;
|
|
|
|
/**
|
|
* The barrier slots for this CU.
|
|
*/
|
|
std::vector<WFBarrier> wfBarrierSlots;
|
|
/**
|
|
* A set used to easily retrieve a free barrier ID.
|
|
*/
|
|
std::unordered_set<int> freeBarrierIds;
|
|
|
|
// hold the time of the arrival of the first cache block related to
|
|
// a particular GPUDynInst. This is used to calculate the difference
|
|
// between the first and last chace block arrival times.
|
|
std::unordered_map<GPUDynInstPtr, Tick> headTailMap;
|
|
|
|
public:
|
|
void updateInstStats(GPUDynInstPtr gpuDynInst);
|
|
int activeWaves;
|
|
|
|
struct ComputeUnitStats : public statistics::Group
|
|
{
|
|
ComputeUnitStats(statistics::Group *parent, int n_wf);
|
|
|
|
statistics::Scalar vALUInsts;
|
|
statistics::Formula vALUInstsPerWF;
|
|
statistics::Scalar sALUInsts;
|
|
statistics::Formula sALUInstsPerWF;
|
|
statistics::Scalar instCyclesVALU;
|
|
statistics::Scalar instCyclesSALU;
|
|
statistics::Scalar threadCyclesVALU;
|
|
statistics::Formula vALUUtilization;
|
|
statistics::Scalar ldsNoFlatInsts;
|
|
statistics::Formula ldsNoFlatInstsPerWF;
|
|
statistics::Scalar flatVMemInsts;
|
|
statistics::Formula flatVMemInstsPerWF;
|
|
statistics::Scalar flatLDSInsts;
|
|
statistics::Formula flatLDSInstsPerWF;
|
|
statistics::Scalar vectorMemWrites;
|
|
statistics::Formula vectorMemWritesPerWF;
|
|
statistics::Scalar vectorMemReads;
|
|
statistics::Formula vectorMemReadsPerWF;
|
|
statistics::Scalar scalarMemWrites;
|
|
statistics::Formula scalarMemWritesPerWF;
|
|
statistics::Scalar scalarMemReads;
|
|
statistics::Formula scalarMemReadsPerWF;
|
|
|
|
statistics::Formula vectorMemReadsPerKiloInst;
|
|
statistics::Formula vectorMemWritesPerKiloInst;
|
|
statistics::Formula vectorMemInstsPerKiloInst;
|
|
statistics::Formula scalarMemReadsPerKiloInst;
|
|
statistics::Formula scalarMemWritesPerKiloInst;
|
|
statistics::Formula scalarMemInstsPerKiloInst;
|
|
|
|
// Cycles required to send register source (addr and data) from
|
|
// register files to memory pipeline, per SIMD.
|
|
statistics::Vector instCyclesVMemPerSimd;
|
|
statistics::Vector instCyclesScMemPerSimd;
|
|
statistics::Vector instCyclesLdsPerSimd;
|
|
|
|
statistics::Scalar globalReads;
|
|
statistics::Scalar globalWrites;
|
|
statistics::Formula globalMemInsts;
|
|
statistics::Scalar argReads;
|
|
statistics::Scalar argWrites;
|
|
statistics::Formula argMemInsts;
|
|
statistics::Scalar spillReads;
|
|
statistics::Scalar spillWrites;
|
|
statistics::Formula spillMemInsts;
|
|
statistics::Scalar groupReads;
|
|
statistics::Scalar groupWrites;
|
|
statistics::Formula groupMemInsts;
|
|
statistics::Scalar privReads;
|
|
statistics::Scalar privWrites;
|
|
statistics::Formula privMemInsts;
|
|
statistics::Scalar readonlyReads;
|
|
statistics::Scalar readonlyWrites;
|
|
statistics::Formula readonlyMemInsts;
|
|
statistics::Scalar kernargReads;
|
|
statistics::Scalar kernargWrites;
|
|
statistics::Formula kernargMemInsts;
|
|
|
|
statistics::Distribution waveLevelParallelism;
|
|
|
|
// the following stats compute the avg. TLB accesslatency per
|
|
// uncoalesced request (only for data)
|
|
statistics::Scalar tlbRequests;
|
|
statistics::Scalar tlbCycles;
|
|
statistics::Formula tlbLatency;
|
|
// hitsPerTLBLevel[x] are the hits in Level x TLB.
|
|
// x = 0 is the page table.
|
|
statistics::Vector hitsPerTLBLevel;
|
|
|
|
statistics::Scalar ldsBankAccesses;
|
|
statistics::Distribution ldsBankConflictDist;
|
|
|
|
// over all memory instructions executed over all wavefronts
|
|
// how many touched 0-4 pages, 4-8, ..., 60-64 pages
|
|
statistics::Distribution pageDivergenceDist;
|
|
// count of non-flat global memory vector instructions executed
|
|
statistics::Scalar dynamicGMemInstrCnt;
|
|
// count of flat global memory vector instructions executed
|
|
statistics::Scalar dynamicFlatMemInstrCnt;
|
|
statistics::Scalar dynamicLMemInstrCnt;
|
|
|
|
statistics::Scalar wgBlockedDueBarrierAllocation;
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statistics::Scalar wgBlockedDueLdsAllocation;
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// Number of instructions executed, i.e. if 64 (or 32 or 7) lanes are
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// active when the instruction is committed, this number is still
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// incremented by 1
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statistics::Scalar numInstrExecuted;
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// Number of cycles among successive instruction executions across all
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// wavefronts of the same CU
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statistics::Distribution execRateDist;
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// number of individual vector operations executed
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statistics::Scalar numVecOpsExecuted;
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// number of individual f16 vector operations executed
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statistics::Scalar numVecOpsExecutedF16;
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// number of individual f32 vector operations executed
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statistics::Scalar numVecOpsExecutedF32;
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// number of individual f64 vector operations executed
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statistics::Scalar numVecOpsExecutedF64;
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// number of individual FMA 16,32,64 vector operations executed
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statistics::Scalar numVecOpsExecutedFMA16;
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statistics::Scalar numVecOpsExecutedFMA32;
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statistics::Scalar numVecOpsExecutedFMA64;
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// number of individual MAC 16,32,64 vector operations executed
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statistics::Scalar numVecOpsExecutedMAC16;
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statistics::Scalar numVecOpsExecutedMAC32;
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statistics::Scalar numVecOpsExecutedMAC64;
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// number of individual MAD 16,32,64 vector operations executed
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statistics::Scalar numVecOpsExecutedMAD16;
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statistics::Scalar numVecOpsExecutedMAD32;
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statistics::Scalar numVecOpsExecutedMAD64;
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// total number of two op FP vector operations executed
|
|
statistics::Scalar numVecOpsExecutedTwoOpFP;
|
|
// Total cycles that something is running on the GPU
|
|
statistics::Scalar totalCycles;
|
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statistics::Formula vpc; // vector ops per cycle
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statistics::Formula vpc_f16; // vector ops per cycle
|
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statistics::Formula vpc_f32; // vector ops per cycle
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statistics::Formula vpc_f64; // vector ops per cycle
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statistics::Formula ipc; // vector instructions per cycle
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statistics::Distribution controlFlowDivergenceDist;
|
|
statistics::Distribution activeLanesPerGMemInstrDist;
|
|
statistics::Distribution activeLanesPerLMemInstrDist;
|
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// number of vector ALU instructions received
|
|
statistics::Formula numALUInstsExecuted;
|
|
// number of times a WG cannot start due to lack of free VGPRs in SIMDs
|
|
statistics::Scalar numTimesWgBlockedDueVgprAlloc;
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// number of times a WG cannot start due to lack of free SGPRs in SIMDs
|
|
statistics::Scalar numTimesWgBlockedDueSgprAlloc;
|
|
statistics::Scalar numCASOps;
|
|
statistics::Scalar numFailedCASOps;
|
|
statistics::Scalar completedWfs;
|
|
statistics::Scalar completedWGs;
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|
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// distrubtion in latency difference between first and last cache block
|
|
// arrival ticks
|
|
statistics::Distribution headTailLatency;
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|
|
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// Track the amount of interleaving between wavefronts on each SIMD.
|
|
// This stat is sampled using instExecPerSimd to compute the number
|
|
// of instructions that have been executed on a SIMD between a WF
|
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// executing two successive instructions.
|
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statistics::VectorDistribution instInterleave;
|
|
} stats;
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};
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} // namespace gem5
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#endif // __COMPUTE_UNIT_HH__
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