528d184ac7
These registers used to be accessed with a two dimensional index, with one dimension specifying the register, and the second index specifying the element within that register. This change linearizes that index down to one dimension, where the elements of each register are laid out one after the other in sequence. Change-Id: I41110f57b505679a327108369db61c826d24922e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49148 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
137 lines
4.1 KiB
C++
137 lines
4.1 KiB
C++
/*
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* Copyright (c) 2009 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __ARCH_X86_ISA_HH__
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#define __ARCH_X86_ISA_HH__
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#include <iostream>
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#include <string>
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#include "arch/generic/isa.hh"
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#include "arch/x86/pcstate.hh"
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#include "arch/x86/regs/float.hh"
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#include "arch/x86/regs/int.hh"
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#include "arch/x86/regs/misc.hh"
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#include "base/types.hh"
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#include "cpu/reg_class.hh"
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namespace gem5
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{
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class ThreadContext;
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struct X86ISAParams;
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namespace X86ISA
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{
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class ISA : public BaseISA
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{
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private:
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RegVal regVal[NUM_MISCREGS];
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void updateHandyM5Reg(Efer efer, CR0 cr0,
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SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags);
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std::string vendorString;
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public:
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void clear();
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PCStateBase *
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newPCState(Addr new_inst_addr=0) const override
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{
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return new PCState(new_inst_addr);
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}
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using Params = X86ISAParams;
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ISA(const Params &p);
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RegVal readMiscRegNoEffect(int miscReg) const;
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RegVal readMiscReg(int miscReg);
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void setMiscRegNoEffect(int miscReg, RegVal val);
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void setMiscReg(int miscReg, RegVal val);
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RegId
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flattenRegId(const RegId& regId) const
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{
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switch (regId.classValue()) {
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case IntRegClass:
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return RegId(IntRegClass, flattenIntIndex(regId.index()));
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case FloatRegClass:
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return RegId(FloatRegClass, flattenFloatIndex(regId.index()));
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case CCRegClass:
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return RegId(CCRegClass, flattenCCIndex(regId.index()));
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case MiscRegClass:
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return RegId(MiscRegClass, flattenMiscIndex(regId.index()));
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default:
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break;
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}
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return regId;
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}
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int flattenIntIndex(int reg) const { return reg & ~IntFoldBit; }
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int
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flattenFloatIndex(int reg) const
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{
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if (reg >= NUM_FLOATREGS) {
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reg = FLOATREG_STACK(reg - NUM_FLOATREGS,
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regVal[MISCREG_X87_TOP]);
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}
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return reg;
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}
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int flattenVecIndex(int reg) const { return reg; }
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int flattenVecElemIndex(int reg) const { return reg; }
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int flattenVecPredIndex(int reg) const { return reg; }
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int flattenCCIndex(int reg) const { return reg; }
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int flattenMiscIndex(int reg) const { return reg; }
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bool
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inUserMode() const override
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{
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HandyM5Reg m5reg = readMiscRegNoEffect(MISCREG_M5_REG);
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return m5reg.cpl == 3;
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}
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void copyRegsFrom(ThreadContext *src) override;
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void serialize(CheckpointOut &cp) const override;
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void unserialize(CheckpointIn &cp) override;
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void setThreadContext(ThreadContext *_tc) override;
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std::string getVendorString() const;
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};
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} // namespace X86ISA
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} // namespace gem5
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#endif
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