58f69391ca
src/arch/alpha/utility.hh:
src/arch/mips/utility.hh:
src/arch/sparc/utility.hh:
src/arch/x86/utility.hh:
add hook for system to startup the cpu or not... in the case of FS sparc, only the first cpu would get spunup.. the rest sit in an idle state until they get an ipi
src/arch/sparc/isa/decoder.isa:
handle writable bits of strandstatus register in miscregfile
src/arch/sparc/miscregfile.hh:
some constants for the strand status register
src/arch/sparc/ua2005.cc:
properly implement the strand status register
src/dev/sparc/iob.cc:
implement ipi generation properly
src/sim/system.cc:
call into the ISA to start the CPU (or not)
--HG--
extra : convert_revision : 0003b2032337d8a031a9fc044da726dbb2a9e36f
134 lines
4.3 KiB
C++
134 lines
4.3 KiB
C++
/*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#ifndef __ARCH_SPARC_UTILITY_HH__
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#define __ARCH_SPARC_UTILITY_HH__
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#include "arch/sparc/faults.hh"
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#include "arch/sparc/isa_traits.hh"
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#include "arch/sparc/tlb.hh"
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#include "base/misc.hh"
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#include "base/bitfield.hh"
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#include "cpu/thread_context.hh"
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namespace SparcISA
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{
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static inline bool
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inUserMode(ThreadContext *tc)
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{
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return !(tc->readMiscRegNoEffect(MISCREG_PSTATE & (1 << 2)) ||
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tc->readMiscRegNoEffect(MISCREG_HPSTATE & (1 << 2)));
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}
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inline ExtMachInst
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makeExtMI(MachInst inst, ThreadContext * xc) {
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ExtMachInst emi = (MachInst) inst;
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//The I bit, bit 13, is used to figure out where the ASI
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//should come from. Use that in the ExtMachInst. This is
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//slightly redundant, but it removes the need to put a condition
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//into all the execute functions
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if(inst & (1 << 13))
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emi |= (static_cast<ExtMachInst>(xc->readMiscRegNoEffect(MISCREG_ASI))
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<< (sizeof(MachInst) * 8));
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else
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emi |= (static_cast<ExtMachInst>(bits(inst, 12, 5))
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<< (sizeof(MachInst) * 8));
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return emi;
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}
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inline bool isCallerSaveIntegerRegister(unsigned int reg) {
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panic("register classification not implemented");
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return false;
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}
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inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
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panic("register classification not implemented");
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return false;
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}
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inline bool isCallerSaveFloatRegister(unsigned int reg) {
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panic("register classification not implemented");
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return false;
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}
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inline bool isCalleeSaveFloatRegister(unsigned int reg) {
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panic("register classification not implemented");
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return false;
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}
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// Instruction address compression hooks
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inline Addr realPCToFetchPC(const Addr &addr)
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{
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return addr;
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}
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inline Addr fetchPCToRealPC(const Addr &addr)
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{
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return addr;
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}
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// the size of "fetched" instructions (not necessarily the size
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// of real instructions for PISA)
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inline size_t fetchInstSize()
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{
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return sizeof(MachInst);
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}
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/**
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* Function to insure ISA semantics about 0 registers.
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* @param tc The thread context.
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*/
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template <class TC>
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void zeroRegisters(TC *tc);
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inline void initCPU(ThreadContext *tc, int cpuId)
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{
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static Fault por = new PowerOnReset();
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if (cpuId == 0)
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por->invoke(tc);
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}
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inline void startupCPU(ThreadContext *tc, int cpuId)
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{
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#if FULL_SYSTEM
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// Other CPUs will get activated by IPIs
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if (cpuId == 0)
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tc->activate(0);
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#else
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tc->activate(0);
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#endif
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}
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} // namespace SparcISA
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#endif
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