de134bae21
Change-Id: I7c5f4a3a9d82ca4550e833dec2cd576dbe333627 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42203 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com> Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
866 lines
29 KiB
Python
866 lines
29 KiB
Python
# Copyright (c) 2015-2021 Advanced Micro Devices, Inc.
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# All rights reserved.
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#
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# For use for simulation and test purposes only
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are met:
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#
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# 1. Redistributions of source code must retain the above copyright notice,
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# this list of conditions and the following disclaimer.
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#
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# 2. Redistributions in binary form must reproduce the above copyright notice,
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# this list of conditions and the following disclaimer in the documentation
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# and/or other materials provided with the distribution.
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#
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# 3. Neither the name of the copyright holder nor the names of its
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# contributors may be used to endorse or promote products derived from this
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# software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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# POSSIBILITY OF SUCH DAMAGE.
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class Statement(object):
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def __init__(self):
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self.keyword = ''
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class ImportStatement(Statement):
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def __init__(self):
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self.keyword = 'import'
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self.what = ''
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self.name = ''
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class FlagBlock(Statement):
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def __init__(self):
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self.keyword = 'flag'
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self.name = ''
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self.desc = []
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def update(self, ref):
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if ref.tag == 'name':
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self.name = ref.name
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elif ref.tag == 'desc':
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self.desc = ref.desc
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elif ref.tag == 'desc+':
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self.desc = self.desc + ref.desc
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else:
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assert (False), 'error: unexpected FlagBlock.tag' + ref.tag
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self.tag = 'updated'
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class FlagsField(object):
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def __init__(self):
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self.tag = ''
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self.name = ''
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self.private = 0
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self.desc = []
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self.group = ''
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def update(self, ref):
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if ref.tag == 'name':
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self.name = ref.name
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elif ref.tag == 'private':
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self.private = ref.private
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elif ref.tag == 'desc':
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self.desc = ref.desc
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elif ref.tag == 'desc+':
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self.desc = self.desc + ref.desc
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elif ref.tag == 'group':
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self.group = ref.group
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else:
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assert (False), 'error: unexpected FlagsField.tag ' + ref.tag
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self.tag = 'updated'
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class FlagsBlock(Statement):
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def __init__(self):
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self.keyword = 'flags'
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self.clauses = []
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class OpInfo(object):
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def __init__(self):
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self.tag = ''
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self.opr = ''
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self.index = -1
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self.iseq = ''
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self.name = ''
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self.fmt = ''
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self.size = -1
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self.inout = -1
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def __repr__(self):
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text = '\n [\n'
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text += '\topr: ' + repr(self.opr) + ',\n'
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text += '\tindex: ' + repr(self.index) + ',\n'
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text += '\tiseq: ' + repr(self.iseq) + ',\n'
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text += '\tname: ' + repr(self.name) + ',\n'
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text += '\tfmt: ' + repr(self.fmt) + ',\n'
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text += '\tsize: ' + repr(self.size) + ',\n'
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text += '\tinout: ' + repr(self.inout) + '\n'
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text += '\n ]\n'
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return text
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def update(self, ref):
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if ref.tag == 'dst':
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self.opr = ref.opr
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self.index = ref.index
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self.iseq = ref.iseq
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elif ref.tag == 'src':
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self.opr = ref.opr
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self.index = ref.index
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self.iseq = ref.iseq
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elif ref.tag == 'name':
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self.name = ref.name
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elif ref.tag == 'fmt':
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self.fmt = ref.fmt
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elif ref.tag == 'size':
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self.size = ref.size
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elif ref.tag == 'inout':
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self.inout = ref.inout
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else:
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assert (False), 'error: unexpected OpInfo.tag ' + ref.tag
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self.tag = 'updated'
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def match(self, ref):
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if self.opr != ref.opr:
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return False
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if self.index != ref.index:
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return False
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return True
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def override(self, ref):
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if ref.iseq:
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self.iseq = ref.iseq
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if ref.name:
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self.name = ref.name
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if ref.fmt:
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self.fmt = ref.fmt
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if ref.size >= 0:
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self.size = ref.size
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if ref.inout >= 0:
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self.inout = ref.inout
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class Operand(object):
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def __init__(self):
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self.tag = ''
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self.num_dst = -1
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self.num_src = -1
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self.parent_enc = ''
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self.sub_enc = ''
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self.flags = []
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self.dst = []
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self.src = []
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self.when = []
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self.operands = []
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def __repr__(self):
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text = '\tnum_dst: ' + repr(self.num_dst) + ',\n'
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text += '\tnum_src: ' + repr(self.num_src) + ',\n'
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text += '\tparent_enc: ' + repr(self.parent_enc) + ',\n'
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text += '\tsub_enc: ' + repr(self.sub_enc) + ',\n'
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text += '\tflags: ' + repr(self.flags) + ',\n'
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text += '\tdst: ' + repr(self.dst) + ',\n'
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text += '\tsrc: ' + repr(self.src) + ',\n'
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text += '\twhen: ' + repr(self.when) + ',\n'
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text += '\toperands: ' + repr(self.operands) + '\n'
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return text
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def update(self, ref):
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if ref.tag == 'num_dst':
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self.num_dst = ref.num_dst
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elif ref.tag == 'num_src':
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self.num_src = ref.num_src
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elif ref.tag == 'parent_enc':
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self.parent_enc = ref.parent_enc
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elif ref.tag == 'sub_enc':
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self.sub_enc = ref.sub_enc
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elif ref.tag == 'flags':
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self.flags = self.flags + ref.flags
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elif ref.tag == 'dst':
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self.dst = self.dst + ref.dst
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elif ref.tag == 'src':
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self.src = self.src + ref.src
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elif ref.tag == 'when':
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self.when = self.when + ref.when
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elif ref.tag == 'operands':
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self.operands = self.operands + ref.operands
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else:
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assert (False), 'error: unexpected Operand.tag ' + ref.tag
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self.tag = 'updated'
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def override(self, ref):
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if ref.num_dst > 0:
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self.num_dst = ref.num_dst
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if ref.num_src > 0:
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self.num_src = ref.num_src
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for r in ref.dst:
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for s in self.dst:
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if s.match(r):
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s.override(r)
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for r in ref.src:
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for s in self.src:
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if s.match(r):
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s.override(r)
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class WhenBlock(object):
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def __init__(self):
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self.left = ''
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self.right = []
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self.operand = None
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class EncodingBlock(Statement):
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def __init__(self):
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self.keyword = 'encoding'
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self.tag = ''
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self.name = ''
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self.bits = ''
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self.size = -1
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self.desc = []
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self.operands = []
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def update(self, ref):
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if ref.tag == 'name':
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self.name = ref.name
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elif ref.tag == 'bits':
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self.bits = ref.bits
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elif ref.tag == 'size':
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self.size = ref.size
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elif ref.tag == 'desc':
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self.desc = self.desc + ref.desc
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elif ref.tag == 'operands':
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self.operands = self.operands + ref.operands
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else:
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assert (False), 'error: unexpected EncodingBlock.tag ' + ref.tag
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self.tag = 'updated'
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class ConstClause(object):
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def __init__(self):
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self.name = ''
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self.value = 0
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class ConstBlock(Statement):
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def __init__(self):
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self.keyword = 'const'
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self.clauses = []
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class TypeClause(object):
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def __init__(self):
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self.tag = ''
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self.name = ''
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self.v_max = 0
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self.value = 0
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self.dp_only = 0
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self.size = -1
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self.var = False
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self.desc = []
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self.flags = []
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self.src_flags = ''
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self.sp3_desc = []
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self.sp3_name = ''
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self.sp3_ncomp = 0
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self.sp3_num = ''
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self.parent_enc = ''
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self.sub_enc = ''
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self.op_type = ''
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self.fmt = ''
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self.type = ''
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self.range = []
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self.size_bits = -1
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def update(self, ref):
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if ref.tag == 'id_range':
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self.name = ref.name
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self.v_max = ref.v_max
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self.value = ref.value
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elif ref.tag == 'id_number':
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self.name = ref.name
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self.value = ref.value
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elif ref.tag == 'id_var_number':
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self.name = ref.name
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self.value = ref.value
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self.var = ref.var
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elif ref.tag == 'desc':
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self.desc = ref.desc + self.desc
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elif ref.tag == 'desc+':
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self.desc = self.desc + ref.desc
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elif ref.tag == 'flags':
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self.flags = ref.flags + self.flags
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elif ref.tag == 'flags+':
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self.flags = self.flags + ref.flags
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elif ref.tag == 'src_flags':
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self.src_flags = ref.src_flags
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elif ref.tag == 'sp3_desc':
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self.sp3_desc = ref.sp3_desc + self.sp3_desc
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elif ref.tag == 'sp3_desc+':
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self.sp3_desc = self.sp3_desc + ref.sp3_desc
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elif ref.tag == 'sp3_name':
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self.sp3_name = ref.sp3_name
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elif ref.tag == 'sp3_ncomp':
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self.sp3_ncomp = ref.sp3_ncomp
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elif ref.tag == 'sp3_num':
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self.sp3_num = ref.sp3_num
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elif ref.tag == 'parent_enc':
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self.parent_enc = ref.parent_enc
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elif ref.tag == 'sub_enc':
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self.sub_enc = ref.sub_enc
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elif ref.tag == 'op_type':
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self.op_type = ref.op_type
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elif ref.tag == 'dp_only':
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self.dp_only = ref.dp_only
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elif ref.tag == 'size':
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self.size = ref.size
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elif ref.tag == 'fmt':
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self.fmt = ref.fmt
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elif ref.tag == 'type':
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self.type = ref.type
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elif ref.tag == 'range':
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self.range = ref.range
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else:
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assert (False), 'error: unexpected TypeClause.tag ' + ref.tag
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self.tag = 'updated'
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class TypeBlock(Statement):
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def __init__(self):
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self.keyword = 'type'
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self.name = ''
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self.clauses = []
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class InstField(object):
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def __init__(self):
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self.tag = ''
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self.name = ''
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self.v_max = 0
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self.value = 0
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self.desc = ''
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self.type = ''
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self.enc = ''
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def update(self, ref):
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if ref.tag == 'id_range':
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self.name = ref.name
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self.v_max = ref.v_max
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self.value = ref.value
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elif ref.tag == 'id_number':
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self.name = ref.name
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self.value = ref.value
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elif ref.tag == 'desc':
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self.desc = ref.desc
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elif ref.tag == 'type':
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self.type = ref.type
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elif ref.tag == 'enc':
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self.enc = ref.enc
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else:
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assert (False), 'error: unexpected InstField.tag ' + ref.tag
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self.tag = 'updated'
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class InstBlock(Statement):
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def __init__(self):
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self.keyword = 'inst'
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self.tag = ''
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self.name = ''
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self.desc = ''
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self.fields = []
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def update(self, ref):
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if ref.tag == 'name':
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self.name = ref.name
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elif ref.tag == 'desc':
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self.desc = ref.desc
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elif ref.tag == 'fields':
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self.fields = ref.fields
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else:
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assert (False), 'error: unexpected InstBlock.tag ' + ref.tag
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self.tag = 'updated'
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FmtToDetails = {
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'NUM_B8' : ( 'SregU8', 8 ),
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'NUM_I8' : ( 'SregI8', 8 ),
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'NUM_B16' : ( 'SregU16', 16 ),
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'NUM_F16' : ( 'SregF16', 16 ),
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'NUM_B32' : ( 'SregU32', 32 ),
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'NUM_F32' : ( 'SregF32', 32 ),
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'NUM_I32' : ( 'SregI32', 32 ),
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'NUM_U32' : ( 'SregU32', 32 ),
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'NUM_B64' : ( 'SregU64', 64 ),
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'NUM_I64' : ( 'SregI64', 64 ),
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'NUM_F64' : ( 'SregF64', 64 ),
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'NUM_U64' : ( 'SregU64', 64 ),
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'BUF' : ( 'SregU64', 64 ),
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'NUM_B96' : ( 'SregU96', 96 ),
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'NUM_B128' : ( 'SregU128', 128 ),
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'RSRC_SCRATCH' : ( 'SregU128', 128 ),
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'RSRC_SCALAR' : ( 'SregU128', 128 ),
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'IMG' : ( 'SregU256', 256 ),
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}
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# which get method is used to retrieve
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# or set data
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TypeToAccessMethod = {
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# scalar reg file get
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'SregU8' : 'ScalarReg',
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'SregI8' : 'ScalarReg',
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'SregU16' : 'ScalarReg',
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'SregI16' : 'ScalarReg',
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'SregU32' : 'ScalarReg',
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'SregI32' : 'ScalarReg',
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'SregU64' : 'ScalarReg',
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'SregI64' : 'ScalarReg',
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'SregU96' : 'ScalarReg',
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'SregU128' : 'ScalarReg',
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'SregU256' : 'ScalarReg',
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'SregU512' : 'ScalarReg',
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'SregF16' : 'ScalarReg',
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'SregF32' : 'ScalarReg',
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'SregF64' : 'ScalarReg',
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# vector reg file get
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'VregU8' : 'VectorReg',
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'VregI8' : 'VectorReg',
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'VregU16' : 'VectorReg',
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'VregI16' : 'VectorReg',
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'VregU32' : 'VectorReg',
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'VregI32' : 'VectorReg',
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'VregU64' : 'VectorReg',
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'VregI64' : 'VectorReg',
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'VregU96' : 'VectorReg',
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'VregU128' : 'VectorReg',
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'VregU256' : 'VectorReg',
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'VregU512' : 'VectorReg',
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'VregF16' : 'VectorReg',
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'VregF32' : 'VectorReg',
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'VregF64' : 'VectorReg',
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}
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SpecialCtx = {
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'SRC_NOLIT' : 'SrcReg',
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'SRC' : 'SrcReg',
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'SRC_NOLDS' : 'SrcReg',
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'SRC_SIMPLE' : 'SrcReg',
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'EXEC' : 'SpecialReg',
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'VCC' : 'SpecialReg',
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'SCC' : 'SpecialReg',
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'PC' : 'SpecialReg',
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'PRIV' : 'SpecialReg',
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'INST_ATC' : 'SpecialReg',
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'M0' : 'SpecialReg',
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'VSKIP' : 'SpecialReg',
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'PI' : 'SpecialReg',
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'NAN' : 'SpecialReg',
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'INF' : 'SpecialReg',
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'P0' : 'SpecialReg',
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'P10' : 'SpecialReg',
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'P20' : 'SpecialReg',
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'TBA' : 'SpecialReg',
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}
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# for DS fixup
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SuffixToFmt = {
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'_I8' : 'NUM_I8',
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'I32' : 'NUM_I32',
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'I64' : 'NUM_I64'
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}
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EncRegInfoToField = {
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'DS:ADDR:VGPR:vgpr_a' : 'ADDR',
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'MUBUF:ADDR:VGPR:vgpr_a' : 'VADDR',
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'MIMG:ADDR:VGPR:vgpr_a' : 'VADDR',
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}
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RegInfoToField = {
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'D:SDST:sdst' : 'SDST',
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'D:SREG:sdst' : 'SDST',
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'S0:SDST:ssrc' : 'SDST',
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'S:SSRC:ssrc' : 'SSRC0',
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'S0:SREG:ssrc' : 'SSRC0',
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'S0:SSRC:ssrc' : 'SSRC0',
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'S0:SSRC:ssrc_0' : 'SSRC0',
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'S1:SSRC:ssrc_1' : 'SSRC1',
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'SGPR:SREG:sgpr' : '',
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'D:VGPR:vdst' : 'VDST',
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'D:VGPR:vgpr_dst' : 'VDST',
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'S0:SRC:src' : 'SRC0',
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'S0:SRC:src_0' : 'SRC0',
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'S0:SRC_NOLDS:src_0' : 'SRC0',
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'S0:SRC_NOLIT:src_0' : 'SRC0',
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'S0:SRC_NOLIT:src' : 'SRC0',
|
|
'S0:SRC_VGPR:src' : 'SRC0',
|
|
'S:SRC:src' : 'SRC0',
|
|
'S:SRC_NOLIT:src' : 'SRC0',
|
|
'S0:SRC_SIMPLE:src_0' : 'SRC0',
|
|
'S1:SRC_SIMPLE:src_1' : 'SRC1',
|
|
'S2:SRC_SIMPLE:src_2' : 'SRC2',
|
|
'S1:VGPR:src_1' : 'VSRC1',
|
|
'S:VGPR:vgpr_ij' : 'VSRC',
|
|
'S:SRC_VGPR:vgpr_ij' : 'SRC0',
|
|
'S0:SRC_VGPR:vgpr_ij' : 'SRC0',
|
|
'S2:SRC_VGPR:vgpr_add' : 'SRC2',
|
|
'S2:VGPR:src_2' : 'VSRC1',
|
|
'VGPR:VGPR:vgpr' : '',
|
|
'VGPR:SRC:vgpr' : '',
|
|
'VGPR:SRC_VGPR:vgpr' : '',
|
|
'VGPR:SRC_NOLIT:vgpr' : '',
|
|
'MEM:MEM:Mem()' : '',
|
|
'A:VGPR:vgpr_a' : '',
|
|
'B:VGPR:vgpr_a' : '',
|
|
'ADDR:SREG:sgpr_base' : 'SBASE',
|
|
'DATA:SMWR_OFFSET:offset' : 'OFFSET',
|
|
'DATA:SREG:sgpr_data' : 'SDATA',
|
|
'RETURN_DATA:SREG:sgpr_data' : 'SDATA',
|
|
'ADDR_BASE:VGPR:vgpr_a' : 'ADDR',
|
|
'DATA:VGPR:vgpr_d0' : 'DATA0',
|
|
'DATA_0:VGPR:vgpr_d0' : 'DATA0',
|
|
'DATA_1:VGPR:vgpr_d0' : 'DATA0',
|
|
'DATA_2:VGPR:vgpr_d0' : 'DATA0',
|
|
'RETURN_DATA:VGPR:vgpr_rtn' : 'VDST',
|
|
'RETURN_DATA_0:VGPR:vgpr_rtn' : 'VDST',
|
|
'RETURN_DATA_1:VGPR:vgpr_rtn' : 'VDST',
|
|
'DATA2:VGPR:vgpr_d1' : 'DATA1',
|
|
'DATA:SREG:sgpr_r' : 'SRSRC',
|
|
'DATA_0:SREG:sgpr_r' : 'SRSRC',
|
|
'DATA_1:SREG:sgpr_r' : 'SRSRC',
|
|
'DATA_2:SREG:sgpr_r' : 'SRSRC',
|
|
'DATA:SREG:sgpr_dst' : 'SDATA',
|
|
'DATA:VGPR:vgpr_d' : 'VDATA',
|
|
'DATA_0:VGPR:vgpr_d' : 'VDATA',
|
|
'DATA_1:VGPR:vgpr_d' : 'VDATA',
|
|
'DATA_2:VGPR:vgpr_d' : 'VDATA',
|
|
'RETURN_DATA:VGPR:vgpr_d' : 'VDATA',
|
|
'RETURN_DATA_0:VGPR:vgpr_d' : 'VDATA',
|
|
'RETURN_DATA_1:VGPR:vgpr_d' : 'VDATA',
|
|
'ADDR:VGPR:vgpr_addr' : 'ADDR',
|
|
'ADDR:VGPR:vgpr_src' : 'ADDR',
|
|
'DATA:VGPR:vgpr_src' : 'DATA',
|
|
'DATA_0:VGPR:vgpr_src' : 'DATA',
|
|
'DATA_1:VGPR:vgpr_src' : 'DATA',
|
|
'DATA_2:VGPR:vgpr_src' : 'DATA',
|
|
'DATA:VGPR:vgpr_dst' : 'VDST',
|
|
'DATA_0:VGPR:vgpr_dst' : 'VDST',
|
|
'DATA_1:VGPR:vgpr_dst' : 'VDST',
|
|
'DATA_2:VGPR:vgpr_dst' : 'VDST',
|
|
'RETURN_DATA:VGPR:vgpr_dst' : 'VDST',
|
|
'RETURN_DATA_0:VGPR:vgpr_dst' : 'VDST',
|
|
'RETURN_DATA_1:VGPR:vgpr_dst' : 'VDST',
|
|
'D:VCC:vcc' : '-VCC',
|
|
}
|
|
|
|
DataRegisters = ['DATA', 'DATA_0', 'DATA_1', 'DATA_2', 'RETURN_DATA',
|
|
'RETURN_DATA_0', 'RETURN_DATA_1']
|
|
|
|
SpecRegToDetails = {
|
|
'SCC' : ['SCC', '', 'scc', 'SregU32', '', ''],
|
|
'M0' : ['M0', '', 'm0', 'SregU32', '', ''],
|
|
'PRIV' : ['PRIV', '', 'priv', 'SregU32', '', ''],
|
|
'VSKIP' : ['VSKIP', '', 'vskip', 'SregU32', '', ''],
|
|
'INST_ATC' : ['INST_ATC', '', 'atc', 'SregU32', '', ''],
|
|
'VCC' : ['VCC', '', 'vcc', 'SregU64', '', ''],
|
|
'PC' : ['PC', '', 'pc', 'SregU64', '', ''],
|
|
'TBA' : ['TBA', '', 'tba', 'SregU64', '', ''],
|
|
'EXEC' : ['EXEC', '', 'exec', 'SregU64', '', ''],
|
|
'PI' : ['PI', '', 'pi', 'SregF32', '', ''],
|
|
'INF' : ['INF', '', 'inf', 'SregF32', '', ''],
|
|
'NAN' : ['NAN', '', 'nan', 'SregF32', '', ''],
|
|
'P0' : ['P0', '', 'p0', 'SregF32', '', ''],
|
|
'P10' : ['P10', '', 'p10', 'SregF32', '', ''],
|
|
'P20' : ['P20', '', 'p20', 'SregF32', '', ''],
|
|
'offset0' : ['', 'instData.OFFSET0', 'offset0', 'SregU16', '', ''],
|
|
'OFFSET0' : ['', 'instData.OFFSET0', 'offset0', 'SregU16', '', ''],
|
|
'offset1' : ['', 'instData.OFFSET1', 'offset1', 'SregU16', '', ''],
|
|
'OFFSET1' : ['', 'instData.OFFSET1', 'offset1', 'SregU16', '', ''],
|
|
'SIMM16' : ['', 'instData.SIMM16', 'simm16', 'SregI16', '', ''],
|
|
'SIMM4' : ['', 'instData.SSRC1', 'simm4', 'SregU16', '', ''],
|
|
'threadID' : ['', '', 't', 'SregU32', '', ''],
|
|
'cmp' : ['', '', 'cmp', 'SregU64', '', ''],
|
|
'src' : ['', '', 'src', 'SregU64', '', ''],
|
|
'tmp' : ['', '', 'tmp', 'SregU64', '', ''],
|
|
'attr_word' : ['ATTR', '', 'attr_word', 'SregU32', '', ''],
|
|
'K' : ['', 'extData.imm_u32', 'k', 'SregU32', '', '']
|
|
}
|
|
|
|
CoreMethodMap = {
|
|
'getSRC_NOLDS_U32' : 'getSRC_U32',
|
|
'getSRC_NOLDS_I32' : 'getSRC_I32',
|
|
'getSRC_NOLDS_F16' : 'getSRC_F16',
|
|
'getSRC_NOLDS_U16' : 'getSRC_U16',
|
|
'getSRC_NOLIT_F16' : 'getSRC_F16',
|
|
'getSRC_SIMPLE_F16' : 'getSRC_F16',
|
|
'getSRC_NOLIT_F32' : 'getSRC_F32',
|
|
'getSRC_SIMPLE_F32' : 'getSRC_F32',
|
|
'getSRC_NOLIT_F64' : 'getSRC_F64',
|
|
'getSRC_SIMPLE_F64' : 'getSRC_F64',
|
|
'getSRC_NOLIT_U16' : 'getSRC_U16',
|
|
'getSRC_SIMPLE_U16' : 'getSRC_U16',
|
|
'getSRC_NOLIT_U32' : 'getSRC_U32',
|
|
'getSRC_SIMPLE_U32' : 'getSRC_U32',
|
|
'getSRC_NOLIT_U64' : 'getSRC_U64',
|
|
'getSRC_SIMPLE_U64' : 'getSRC_U64',
|
|
'getSRC_NOLIT_I32' : 'getSRC_I32',
|
|
'getSRC_SIMPLE_I32' : 'getSRC_I32',
|
|
'getSRC_VGPR_F32' : 'getSRC_F32',
|
|
'getSRC_SIMPLE_I64' : 'getSRC_I64'
|
|
}
|
|
|
|
KnownExceptions = [
|
|
'Inst_SOP2__S_CBRANCH_G_FORK',
|
|
'Inst_SOPK__S_ADDK_I32',
|
|
'Inst_SOPK__S_CBRANCH_I_FORK',
|
|
'Inst_SOPK__S_GETREG_B32',
|
|
'Inst_SOP1__S_CBRANCH_JOIN',
|
|
'Inst_SOPP__S_CBRANCH_CDBGSYS',
|
|
'Inst_SOPP__S_CBRANCH_CDBGUSER',
|
|
'Inst_SOPP__S_CBRANCH_CDBGSYS_OR_USER',
|
|
'Inst_SOPP__S_CBRANCH_CDBGSYS_AND_USER',
|
|
'Inst_SOPP__S_SET_GPR_IDX_MODE',
|
|
'Inst_VOP1__V_CVT_OFF_F32_I4',
|
|
'Inst_VOP1__V_FFBH_U32',
|
|
'Inst_VOP1__V_FFBL_B32',
|
|
'Inst_VOP1__V_FFBH_I32',
|
|
'Inst_VOPC__V_CMP_CLASS_F32',
|
|
'Inst_VOPC__V_CMPX_CLASS_F32',
|
|
'Inst_VOPC__V_CMP_CLASS_F64',
|
|
'Inst_VOPC__V_CMPX_CLASS_F64',
|
|
'Inst_VOPC__V_CMP_CLASS_F16',
|
|
'Inst_VOPC__V_CMPX_CLASS_F16',
|
|
'Inst_VINTRP__V_INTERP_MOV_F32',
|
|
'Inst_VOP3__V_CMP_CLASS_F32',
|
|
'Inst_VOP3__V_CMPX_CLASS_F32',
|
|
'Inst_VOP3__V_CMP_CLASS_F64',
|
|
'Inst_VOP3__V_CMPX_CLASS_F64',
|
|
'Inst_VOP3__V_CMP_CLASS_F16',
|
|
'Inst_VOP3__V_CMPX_CLASS_F16',
|
|
'Inst_VOP3__V_CVT_OFF_F32_I4',
|
|
'Inst_VOP3__V_FFBH_U32',
|
|
'Inst_VOP3__V_FFBL_B32',
|
|
'Inst_VOP3__V_FFBH_I32',
|
|
'Inst_VOP3__V_CUBEID_F32',
|
|
'Inst_VOP3__V_CUBESC_F32',
|
|
'Inst_VOP3__V_CUBETC_F32',
|
|
'Inst_VOP3__V_CUBEMA_F32',
|
|
'Inst_VOP3__V_DIV_FIXUP_F32',
|
|
'Inst_VOP3__V_DIV_FIXUP_F64',
|
|
'Inst_VOP3__V_DIV_SCALE_F32',
|
|
'Inst_VOP3__V_DIV_SCALE_F64',
|
|
'Inst_VOP3__V_DIV_FMAS_F32',
|
|
'Inst_VOP3__V_DIV_FMAS_F64',
|
|
'Inst_VOP3__V_MSAD_U8',
|
|
'Inst_VOP3__V_QSAD_PK_U16_U8',
|
|
'Inst_VOP3__V_MQSAD_PK_U16_U8',
|
|
'Inst_VOP3__V_MQSAD_U32_U8',
|
|
'Inst_VOP3__V_PERM_B32',
|
|
'Inst_VOP3__V_DIV_FIXUP_F16',
|
|
'Inst_VOP3__V_CVT_PKACCUM_U8_F32',
|
|
'Inst_VOP3__V_INTERP_MOV_F32',
|
|
'Inst_VOP3__V_INTERP_P1LV_F16',
|
|
'Inst_VOP3__V_MBCNT_LO_U32_B32',
|
|
'Inst_VOP3__V_MBCNT_HI_U32_B32',
|
|
'Inst_VOP3__V_TRIG_PREOP_F64',
|
|
'Inst_VOP3__V_CVT_PKNORM_I16_F32',
|
|
'Inst_VOP3__V_CVT_PKNORM_U16_F32',
|
|
'Inst_VOP3__V_CVT_PKRTZ_F16_F32',
|
|
'Inst_VOP3__V_CVT_PK_U16_U32',
|
|
'Inst_VOP3__V_CVT_PK_I16_I32',
|
|
'Inst_DS__DS_READ_U8',
|
|
'Inst_DS__DS_READ_U16',
|
|
'Inst_DS__DS_SWIZZLE_B32',
|
|
'Inst_DS__DS_GWS_BARRIER',
|
|
'Inst_DS__DS_CONSUME',
|
|
'Inst_DS__DS_APPEND',
|
|
'Inst_DS__DS_ORDERED_COUNT',
|
|
'Inst_MIMG__IMAGE_GATHER4',
|
|
'Inst_MIMG__IMAGE_GATHER4_CL',
|
|
'Inst_MIMG__IMAGE_GATHER4_L',
|
|
'Inst_MIMG__IMAGE_GATHER4_B',
|
|
'Inst_MIMG__IMAGE_GATHER4_B_CL',
|
|
'Inst_MIMG__IMAGE_GATHER4_LZ',
|
|
'Inst_MIMG__IMAGE_GATHER4_C',
|
|
'Inst_MIMG__IMAGE_GATHER4_C_CL',
|
|
'Inst_MIMG__IMAGE_GATHER4_C_L',
|
|
'Inst_MIMG__IMAGE_GATHER4_C_B',
|
|
'Inst_MIMG__IMAGE_GATHER4_C_B_CL',
|
|
'Inst_MIMG__IMAGE_GATHER4_C_LZ'
|
|
]
|
|
|
|
KnownEmpty = [
|
|
'Inst_SOPK__S_SETREG_B32',
|
|
'Inst_SOPK__S_SETREG_IMM32_B32',
|
|
'Inst_SOPP__S_WAKEUP',
|
|
'Inst_SOPP__S_BARRIER',
|
|
'Inst_SOPP__S_SETKILL',
|
|
'Inst_SOPP__S_WAITCNT',
|
|
'Inst_SOPP__S_SETHALT',
|
|
'Inst_SOPP__S_SLEEP',
|
|
'Inst_SOPP__S_SETPRIO',
|
|
'Inst_SOPP__S_SENDMSG',
|
|
'Inst_SOPP__S_SENDMSGHALT',
|
|
'Inst_SOPP__S_ICACHE_INV',
|
|
'Inst_SOPP__S_INCPERFLEVEL',
|
|
'Inst_SOPP__S_DECPERFLEVEL',
|
|
'Inst_SOPP__S_TTRACEDATA',
|
|
'Inst_SOPP__S_SET_GPR_IDX_OFF',
|
|
'Inst_SMEM__S_DCACHE_INV',
|
|
'Inst_SMEM__S_DCACHE_WB',
|
|
'Inst_SMEM__S_DCACHE_INV_VOL',
|
|
'Inst_SMEM__S_DCACHE_WB_VOL',
|
|
'Inst_SMEM__S_MEMTIME',
|
|
'Inst_SMEM__S_MEMREALTIME',
|
|
'Inst_SMEM__S_ATC_PROBE',
|
|
'Inst_SMEM__S_ATC_PROBE_BUFFER',
|
|
'Inst_VOP1__V_READFIRSTLANE_B32',
|
|
'Inst_VOP1__V_FREXP_EXP_I32_F64',
|
|
'Inst_VOP1__V_FREXP_MANT_F64',
|
|
'Inst_VOP1__V_FRACT_F64',
|
|
'Inst_VOP1__V_CLREXCP',
|
|
'Inst_VOP1__V_RCP_F16',
|
|
'Inst_VOP1__V_SQRT_F16',
|
|
'Inst_VOP1__V_RSQ_F16',
|
|
'Inst_VOP1__V_LOG_F16',
|
|
'Inst_VOP1__V_EXP_F16',
|
|
'Inst_VOP1__V_FREXP_MANT_F16',
|
|
'Inst_VOP1__V_FREXP_EXP_I16_F16',
|
|
'Inst_VOP3__V_FREXP_EXP_I32_F64',
|
|
'Inst_VOP3__V_FREXP_MANT_F64',
|
|
'Inst_VOP3__V_FRACT_F64',
|
|
'Inst_VOP3__V_CLREXCP',
|
|
'Inst_VOP3__V_RCP_F16',
|
|
'Inst_VOP3__V_SQRT_F16',
|
|
'Inst_VOP3__V_RSQ_F16',
|
|
'Inst_VOP3__V_LOG_F16',
|
|
'Inst_VOP3__V_EXP_F16',
|
|
'Inst_VOP3__V_FREXP_MANT_F16',
|
|
'Inst_VOP3__V_FREXP_EXP_I16_F16',
|
|
'Inst_VOP3__V_READLANE_B32',
|
|
'Inst_VOP3__V_WRITELANE_B32',
|
|
'Inst_DS__DS_WRXCHG2_RTN_B32',
|
|
'Inst_DS__DS_WRXCHG2ST64_RTN_B32',
|
|
'Inst_DS__DS_PERMUTE_B32',
|
|
'Inst_DS__DS_BPERMUTE_B32',
|
|
'Inst_DS__DS_WRXCHG2_RTN_B64',
|
|
'Inst_DS__DS_WRXCHG2ST64_RTN_B64',
|
|
'Inst_DS__DS_CONDXCHG32_RTN_B64',
|
|
'Inst_DS__DS_GWS_SEMA_RELEASE_ALL',
|
|
'Inst_DS__DS_GWS_INIT',
|
|
'Inst_DS__DS_GWS_SEMA_V',
|
|
'Inst_DS__DS_GWS_SEMA_BR',
|
|
'Inst_DS__DS_GWS_SEMA_P',
|
|
'Inst_DS__DS_READ_B96',
|
|
'Inst_DS__DS_READ_B128',
|
|
'Inst_MUBUF__BUFFER_LOAD_FORMAT_X',
|
|
'Inst_MUBUF__BUFFER_LOAD_FORMAT_XY',
|
|
'Inst_MUBUF__BUFFER_LOAD_FORMAT_XYZ',
|
|
'Inst_MUBUF__BUFFER_LOAD_FORMAT_XYZW',
|
|
'Inst_MUBUF__BUFFER_STORE_FORMAT_X',
|
|
'Inst_MUBUF__BUFFER_STORE_FORMAT_XY',
|
|
'Inst_MUBUF__BUFFER_STORE_FORMAT_XYZ',
|
|
'Inst_MUBUF__BUFFER_STORE_FORMAT_XYZW',
|
|
'Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_X',
|
|
'Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XY',
|
|
'Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZ',
|
|
'Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZW',
|
|
'Inst_MUBUF__BUFFER_STORE_FORMAT_D16_X',
|
|
'Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XY',
|
|
'Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XYZ',
|
|
'Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XYZW',
|
|
'Inst_MUBUF__BUFFER_LOAD_UBYTE',
|
|
'Inst_MUBUF__BUFFER_LOAD_SBYTE',
|
|
'Inst_MUBUF__BUFFER_LOAD_USHORT',
|
|
'Inst_MUBUF__BUFFER_LOAD_SSHORT',
|
|
'Inst_MUBUF__BUFFER_STORE_BYTE',
|
|
'Inst_MUBUF__BUFFER_STORE_SHORT',
|
|
'Inst_MUBUF__BUFFER_STORE_LDS_DWORD',
|
|
'Inst_MUBUF__BUFFER_WBINVL1',
|
|
'Inst_MUBUF__BUFFER_WBINVL1_VOL',
|
|
'Inst_MTBUF__TBUFFER_LOAD_FORMAT_X',
|
|
'Inst_MTBUF__TBUFFER_LOAD_FORMAT_XY',
|
|
'Inst_MTBUF__TBUFFER_LOAD_FORMAT_XYZ',
|
|
'Inst_MTBUF__TBUFFER_LOAD_FORMAT_XYZW',
|
|
'Inst_MTBUF__TBUFFER_STORE_FORMAT_X',
|
|
'Inst_MTBUF__TBUFFER_STORE_FORMAT_XY',
|
|
'Inst_MTBUF__TBUFFER_STORE_FORMAT_XYZ',
|
|
'Inst_MTBUF__TBUFFER_STORE_FORMAT_XYZW',
|
|
'Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_X',
|
|
'Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XY',
|
|
'Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZ',
|
|
'Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZW',
|
|
'Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_X',
|
|
'Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XY',
|
|
'Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZ',
|
|
'Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZW',
|
|
'Inst_MIMG__IMAGE_LOAD',
|
|
'Inst_MIMG__IMAGE_LOAD_MIP',
|
|
'Inst_MIMG__IMAGE_LOAD_PCK',
|
|
'Inst_MIMG__IMAGE_LOAD_PCK_SGN',
|
|
'Inst_MIMG__IMAGE_LOAD_MIP_PCK',
|
|
'Inst_MIMG__IMAGE_LOAD_MIP_PCK_SGN',
|
|
'Inst_MIMG__IMAGE_STORE',
|
|
'Inst_MIMG__IMAGE_STORE_MIP',
|
|
'Inst_MIMG__IMAGE_STORE_PCK',
|
|
'Inst_MIMG__IMAGE_STORE_MIP_PCK',
|
|
'Inst_MIMG__IMAGE_GET_RESINFO',
|
|
'Inst_MIMG__IMAGE_SAMPLE',
|
|
'Inst_MIMG__IMAGE_SAMPLE_CL',
|
|
'Inst_MIMG__IMAGE_SAMPLE_D',
|
|
'Inst_MIMG__IMAGE_SAMPLE_D_CL',
|
|
'Inst_MIMG__IMAGE_SAMPLE_L',
|
|
'Inst_MIMG__IMAGE_SAMPLE_B',
|
|
'Inst_MIMG__IMAGE_SAMPLE_B_CL',
|
|
'Inst_MIMG__IMAGE_SAMPLE_LZ',
|
|
'Inst_MIMG__IMAGE_SAMPLE_C',
|
|
'Inst_MIMG__IMAGE_SAMPLE_C_CL',
|
|
'Inst_MIMG__IMAGE_SAMPLE_C_D',
|
|
'Inst_MIMG__IMAGE_SAMPLE_C_D_CL',
|
|
'Inst_MIMG__IMAGE_SAMPLE_C_L',
|
|
'Inst_MIMG__IMAGE_SAMPLE_C_B',
|
|
'Inst_MIMG__IMAGE_SAMPLE_C_B_CL',
|
|
'Inst_MIMG__IMAGE_SAMPLE_C_LZ',
|
|
'Inst_MIMG__IMAGE_SAMPLE_O',
|
|
'Inst_MIMG__IMAGE_SAMPLE_CL_O',
|
|
'Inst_MIMG__IMAGE_SAMPLE_D_O',
|
|
'Inst_MIMG__IMAGE_SAMPLE_D_CL_O',
|
|
'Inst_MIMG__IMAGE_SAMPLE_L_O',
|
|
'Inst_MIMG__IMAGE_SAMPLE_B_O',
|
|
'Inst_MIMG__IMAGE_SAMPLE_B_CL_O',
|
|
'Inst_MIMG__IMAGE_SAMPLE_LZ_O',
|
|
'Inst_MIMG__IMAGE_SAMPLE_C_O',
|
|
'Inst_MIMG__IMAGE_SAMPLE_C_CL_O',
|
|
'Inst_MIMG__IMAGE_SAMPLE_C_D_O',
|
|
'Inst_MIMG__IMAGE_SAMPLE_C_D_CL_O',
|
|
'Inst_MIMG__IMAGE_SAMPLE_C_L_O',
|
|
'Inst_MIMG__IMAGE_SAMPLE_C_B_O',
|
|
'Inst_MIMG__IMAGE_SAMPLE_C_B_CL_O',
|
|
'Inst_MIMG__IMAGE_SAMPLE_C_LZ_O',
|
|
'Inst_MIMG__IMAGE_GATHER4_O',
|
|
'Inst_MIMG__IMAGE_GATHER4_CL_O',
|
|
'Inst_MIMG__IMAGE_GATHER4_L_O',
|
|
'Inst_MIMG__IMAGE_GATHER4_B_O',
|
|
'Inst_MIMG__IMAGE_GATHER4_B_CL_O',
|
|
'Inst_MIMG__IMAGE_GATHER4_LZ_O',
|
|
'Inst_MIMG__IMAGE_GATHER4_C_O',
|
|
'Inst_MIMG__IMAGE_GATHER4_C_CL_O',
|
|
'Inst_MIMG__IMAGE_GATHER4_C_L_O',
|
|
'Inst_MIMG__IMAGE_GATHER4_C_B_O',
|
|
'Inst_MIMG__IMAGE_GATHER4_C_B_CL_O',
|
|
'Inst_MIMG__IMAGE_GATHER4_C_LZ_O',
|
|
'Inst_MIMG__IMAGE_GET_LOD',
|
|
'Inst_MIMG__IMAGE_SAMPLE_CD',
|
|
'Inst_MIMG__IMAGE_SAMPLE_CD_CL',
|
|
'Inst_MIMG__IMAGE_SAMPLE_C_CD',
|
|
'Inst_MIMG__IMAGE_SAMPLE_C_CD_CL',
|
|
'Inst_MIMG__IMAGE_SAMPLE_CD_O',
|
|
'Inst_MIMG__IMAGE_SAMPLE_CD_CL_O',
|
|
'Inst_MIMG__IMAGE_SAMPLE_C_CD_O',
|
|
'Inst_MIMG__IMAGE_SAMPLE_C_CD_CL_O',
|
|
'Inst_EXP__EXP',
|
|
'Inst_FLAT__FLAT_LOAD_UBYTE',
|
|
'Inst_FLAT__FLAT_LOAD_SBYTE',
|
|
'Inst_FLAT__FLAT_LOAD_USHORT',
|
|
'Inst_FLAT__FLAT_LOAD_SSHORT',
|
|
'Inst_FLAT__FLAT_STORE_BYTE',
|
|
'Inst_FLAT__FLAT_STORE_SHORT',
|
|
]
|