6bbde8fbb8
The top level AMDGPUDevice currently reads/writes all unknown registers to/from a map containing the previously written value. This is intended as a way to handle registers that are not part of the model but the driver requires for functionality. Since this is at the top level, it can mask changes to register values which do not go through the same interface. For example, reading an MMIO, changing via PM4 queue, and reading again returns the stale cached value. This commit removes the usage of the regs map in AMDGPUDevice, implements some important MMIOs that were previously handled by it, and moves the unknown register handling to the NBIO aperture only. To reduce the number of additional MMIOs to implement, the display manager in vega10 is now disabled. Change-Id: Iff0a599dd82d663c7e710b79c6ef6d0ad1fc44a2
87 lines
2.8 KiB
C++
87 lines
2.8 KiB
C++
/*
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* Copyright (c) 2023 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "dev/amdgpu/amdgpu_gfx.hh"
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#include "mem/packet_access.hh"
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#include "sim/core.hh"
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namespace gem5
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{
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AMDGPUGfx::AMDGPUGfx()
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{
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for (int i = 0; i < SCRATCH_REGS; ++i) {
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scratchRegs[i] = 0;
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}
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}
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void
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AMDGPUGfx::readMMIO(PacketPtr pkt, Addr offset)
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{
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switch (offset) {
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case AMDGPU_MM_RLC_GPU_CLOCK_COUNT_LSB:
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pkt->setLE<uint32_t>(captured_clock_count);
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break;
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case AMDGPU_MM_RLC_GPU_CLOCK_COUNT_MSB:
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pkt->setLE<uint32_t>(captured_clock_count >> 32);
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break;
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case AMDGPU_MM_SCRATCH_REG0:
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pkt->setLE<uint32_t>(scratchRegs[0]);
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break;
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default:
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break;
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}
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}
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void
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AMDGPUGfx::writeMMIO(PacketPtr pkt, Addr offset)
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{
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switch (offset) {
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case AMDGPU_MM_RLC_CAPTURE_GPU_CLOCK_COUNT:
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// Use gem5 Ticks in nanoseconds are the counter. The first capture
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// is expected to return zero.
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if (captured_clock_count == 1) {
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captured_clock_count = 0;
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} else {
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captured_clock_count = curTick() / sim_clock::as_int::ns;
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}
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break;
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case AMDGPU_MM_SCRATCH_REG0:
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scratchRegs[0] = pkt->getLE<uint32_t>();
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break;
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default:
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break;
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}
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}
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} // namespace gem5
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