d11c40dcac
This ensures `isort` is applied to all files in the repo. Change-Id: Ib7ced1c924ef1639542bf0d1a01c5737f6ba43e9
197 lines
8.0 KiB
Python
197 lines
8.0 KiB
Python
# Copyright (c) 2013 ARM Limited
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# All rights reserved
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Copyright (c) 2005-2007 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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from m5.objects.Device import DmaDevice
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from m5.objects.PciHost import PciHost
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from m5.params import *
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from m5.proxy import *
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from m5.SimObject import SimObject
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class PciBar(SimObject):
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type = "PciBar"
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cxx_class = "gem5::PciBar"
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cxx_header = "dev/pci/device.hh"
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abstract = True
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class PciBarNone(PciBar):
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type = "PciBarNone"
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cxx_class = "gem5::PciBarNone"
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cxx_header = "dev/pci/device.hh"
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class PciIoBar(PciBar):
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type = "PciIoBar"
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cxx_class = "gem5::PciIoBar"
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cxx_header = "dev/pci/device.hh"
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size = Param.MemorySize32("IO region size")
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class PciLegacyIoBar(PciIoBar):
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type = "PciLegacyIoBar"
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cxx_class = "gem5::PciLegacyIoBar"
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cxx_header = "dev/pci/device.hh"
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addr = Param.UInt32("Legacy IO address")
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# To set up a 64 bit memory BAR, put a PciMemUpperBar immediately after
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# a PciMemBar. The pair will take up the right number of BARs, and will be
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# recognized by the device and turned into a 64 bit BAR when the config is
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# consumed.
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class PciMemBar(PciBar):
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type = "PciMemBar"
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cxx_class = "gem5::PciMemBar"
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cxx_header = "dev/pci/device.hh"
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size = Param.MemorySize("Memory region size")
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class PciMemUpperBar(PciBar):
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type = "PciMemUpperBar"
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cxx_class = "gem5::PciMemUpperBar"
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cxx_header = "dev/pci/device.hh"
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class PciDevice(DmaDevice):
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type = "PciDevice"
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cxx_class = "gem5::PciDevice"
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cxx_header = "dev/pci/device.hh"
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abstract = True
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host = Param.PciHost(Parent.any, "PCI host")
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pci_bus = Param.Int("PCI bus")
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pci_dev = Param.Int("PCI device number")
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pci_func = Param.Int("PCI function code")
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pio_latency = Param.Latency("30ns", "Programmed IO latency")
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config_latency = Param.Latency("20ns", "Config read or write latency")
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VendorID = Param.UInt16("Vendor ID")
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DeviceID = Param.UInt16("Device ID")
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Command = Param.UInt16(0, "Command")
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Status = Param.UInt16(0, "Status")
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Revision = Param.UInt8(0, "Device")
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ProgIF = Param.UInt8(0, "Programming Interface")
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SubClassCode = Param.UInt8(0, "Sub-Class Code")
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ClassCode = Param.UInt8(0, "Class Code")
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CacheLineSize = Param.UInt8(0, "System Cacheline Size")
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LatencyTimer = Param.UInt8(0, "PCI Latency Timer")
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HeaderType = Param.UInt8(0, "PCI Header Type")
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BIST = Param.UInt8(0, "Built In Self Test")
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BAR0 = Param.PciBar(PciBarNone(), "Base address register 0")
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BAR1 = Param.PciBar(PciBarNone(), "Base address register 1")
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BAR2 = Param.PciBar(PciBarNone(), "Base address register 2")
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BAR3 = Param.PciBar(PciBarNone(), "Base address register 3")
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BAR4 = Param.PciBar(PciBarNone(), "Base address register 4")
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BAR5 = Param.PciBar(PciBarNone(), "Base address register 5")
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CardbusCIS = Param.UInt32(0x00, "Cardbus Card Information Structure")
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SubsystemID = Param.UInt16(0x00, "Subsystem ID")
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SubsystemVendorID = Param.UInt16(0x00, "Subsystem Vendor ID")
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ExpansionROM = Param.UInt32(0x00, "Expansion ROM Base Address")
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CapabilityPtr = Param.UInt8(0x00, "Capability List Pointer offset")
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InterruptLine = Param.UInt8(0x00, "Interrupt Line")
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InterruptPin = Param.UInt8(0x00, "Interrupt Pin")
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MaximumLatency = Param.UInt8(0x00, "Maximum Latency")
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MinimumGrant = Param.UInt8(0x00, "Minimum Grant")
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# Capabilities List structures for PCIe devices
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# PMCAP - PCI Power Management Capability
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PMCAPBaseOffset = Param.UInt8(
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0x00, "Base offset of PMCAP in PCI Config space"
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)
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PMCAPNextCapability = Param.UInt8(0x00, "Pointer to next capability block")
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PMCAPCapId = Param.UInt8(
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0x00, "Specifies this is the Power Management capability"
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)
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PMCAPCapabilities = Param.UInt16(
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0x0000, "PCI Power Management Capabilities Register"
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)
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PMCAPCtrlStatus = Param.UInt16(
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0x0000, "PCI Power Management Control and Status"
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)
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# MSICAP - Message Signaled Interrupt Capability
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MSICAPBaseOffset = Param.UInt8(
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0x00, "Base offset of MSICAP in PCI Config space"
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)
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MSICAPNextCapability = Param.UInt8(
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0x00, "Pointer to next capability block"
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)
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MSICAPCapId = Param.UInt8(0x00, "Specifies this is the MSI Capability")
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MSICAPMsgCtrl = Param.UInt16(0x0000, "MSI Message Control")
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MSICAPMsgAddr = Param.UInt32(0x00000000, "MSI Message Address")
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MSICAPMsgUpperAddr = Param.UInt32(0x00000000, "MSI Message Upper Address")
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MSICAPMsgData = Param.UInt16(0x0000, "MSI Message Data")
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MSICAPMaskBits = Param.UInt32(0x00000000, "MSI Interrupt Mask Bits")
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MSICAPPendingBits = Param.UInt32(0x00000000, "MSI Pending Bits")
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# MSIXCAP - MSI-X Capability
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MSIXCAPBaseOffset = Param.UInt8(
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0x00, "Base offset of MSIXCAP in PCI Config space"
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)
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MSIXCAPNextCapability = Param.UInt8(
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0x00, "Pointer to next capability block"
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)
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MSIXCAPCapId = Param.UInt8(0x00, "Specifices this the MSI-X Capability")
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MSIXMsgCtrl = Param.UInt16(0x0000, "MSI-X Message Control")
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MSIXTableOffset = Param.UInt32(
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0x00000000, "MSI-X Table Offset and Table BIR"
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)
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MSIXPbaOffset = Param.UInt32(0x00000000, "MSI-X PBA Offset and PBA BIR")
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# PXCAP - PCI Express Capability
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PXCAPBaseOffset = Param.UInt8(
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0x00, "Base offset of PXCAP in PCI Config space"
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)
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PXCAPNextCapability = Param.UInt8(0x00, "Pointer to next capability block")
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PXCAPCapId = Param.UInt8(0x00, "Specifies this is the PCIe Capability")
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PXCAPCapabilities = Param.UInt16(0x0000, "PCIe Capabilities")
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PXCAPDevCapabilities = Param.UInt32(0x00000000, "PCIe Device Capabilities")
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PXCAPDevCtrl = Param.UInt16(0x0000, "PCIe Device Control")
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PXCAPDevStatus = Param.UInt16(0x0000, "PCIe Device Status")
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PXCAPLinkCap = Param.UInt32(0x00000000, "PCIe Link Capabilities")
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PXCAPLinkCtrl = Param.UInt16(0x0000, "PCIe Link Control")
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PXCAPLinkStatus = Param.UInt16(0x0000, "PCIe Link Status")
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PXCAPDevCap2 = Param.UInt32(0x00000000, "PCIe Device Capabilities 2")
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PXCAPDevCtrl2 = Param.UInt32(0x00000000, "PCIe Device Control 2")
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