dd20be6ca9
The CorePairs in MOESI_AMD_Base round up the number of CPUs when creating CPU sequencers. If the CPU count is an odd number, this was causing the Disjoint_VIPER config to connect a sequencer that does not exist. As a result the crossbar was waiting for a range change from the sequencer but it never arrived, causing an assert. This patch fixes this by conditionally connecting CPU sequencers to the PIO port only if the ID is less than the number of CPUs. Change-Id: I2280c0048492d43528429a947a726871f1c23ca7 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57531 Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com> Maintainer: Matt Sinclair <mattdsinclair@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
197 lines
8.0 KiB
Python
197 lines
8.0 KiB
Python
# Copyright (c) 2021 Advanced Micro Devices, Inc.
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are met:
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#
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# 1. Redistributions of source code must retain the above copyright notice,
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# this list of conditions and the following disclaimer.
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#
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# 2. Redistributions in binary form must reproduce the above copyright notice,
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# this list of conditions and the following disclaimer in the documentation
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# and/or other materials provided with the distribution.
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#
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# 3. Neither the name of the copyright holder nor the names of its
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# contributors may be used to endorse or promote products derived from this
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# software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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# POSSIBILITY OF SUCH DAMAGE.
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from m5.defines import buildEnv
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from m5.objects import *
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from m5.util import fatal
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from example.gpufs.DisjointNetwork import *
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from ruby.GPU_VIPER import *
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from ruby import Ruby
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class DummySystem():
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def __init__(self, mem_ranges):
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self.mem_ctrls = []
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self.mem_ranges = mem_ranges
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class Disjoint_VIPER(RubySystem):
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def __init__(self):
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if buildEnv['PROTOCOL'] != "GPU_VIPER":
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fatal("This ruby config only supports the GPU_VIPER protocol")
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super(Disjoint_VIPER, self).__init__()
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def create(self, options, system, piobus, dma_devices):
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# Disjoint network topology
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if "garnet" in options.network:
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self.network_cpu = DisjointGarnet(self)
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self.network_gpu = DisjointGarnet(self)
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else:
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self.network_cpu = DisjointSimple(self)
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self.network_gpu = DisjointSimple(self)
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# Construct CPU controllers
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cpu_dir_nodes = \
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construct_dirs(options, system, self, self.network_cpu)
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(cp_sequencers, cp_cntrl_nodes) = \
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construct_corepairs(options, system, self, self.network_cpu)
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# Construct GPU controllers
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(tcp_sequencers, tcp_cntrl_nodes) = \
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construct_tcps(options, system, self, self.network_gpu)
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(sqc_sequencers, sqc_cntrl_nodes) = \
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construct_sqcs(options, system, self, self.network_gpu)
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(scalar_sequencers, scalar_cntrl_nodes) = \
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construct_scalars(options, system, self, self.network_gpu)
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tcc_cntrl_nodes = \
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construct_tccs(options, system, self, self.network_gpu)
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# Construct CPU memories
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Ruby.setup_memory_controllers(system, self, cpu_dir_nodes, options)
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# Construct GPU memories
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(gpu_dir_nodes, gpu_mem_ctrls) = \
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construct_gpudirs(options, system, self, self.network_gpu)
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# Configure the directories based on which network they are in
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for cpu_dir_node in cpu_dir_nodes:
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cpu_dir_node.CPUonly = True
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cpu_dir_node.GPUonly = False
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for gpu_dir_node in gpu_dir_nodes:
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gpu_dir_node.CPUonly = False
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gpu_dir_node.GPUonly = True
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# Set access backing store if specified
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if options.access_backing_store:
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self.access_backing_store = True
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# Assign the memory controllers to the system
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cpu_abstract_mems = []
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for mem_ctrl in system.mem_ctrls:
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cpu_abstract_mems.append(mem_ctrl.dram)
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system.memories = cpu_abstract_mems
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gpu_abstract_mems = []
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for mem_ctrl in gpu_mem_ctrls:
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gpu_abstract_mems.append(mem_ctrl.dram)
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system.pc.south_bridge.gpu.memories = gpu_abstract_mems
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# Setup DMA controllers
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gpu_dma_types = ["VegaPagetableWalker", "AMDGPUMemoryManager"]
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cpu_dma_ctrls = []
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gpu_dma_ctrls = []
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dma_cntrls = []
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for i, dma_device in enumerate(dma_devices):
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dma_seq = DMASequencer(version=i, ruby_system=self)
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dma_cntrl = DMA_Controller(version=i, dma_sequencer=dma_seq,
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ruby_system=self)
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# Handle inconsistently named ports on various DMA devices:
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if not hasattr(dma_device, 'type'):
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# IDE doesn't have a .type but seems like everything else does.
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dma_seq.in_ports = dma_device
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elif dma_device.type in gpu_dma_types:
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dma_seq.in_ports = dma_device.port
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else:
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dma_seq.in_ports = dma_device.dma
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if hasattr(dma_device, 'type') and \
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dma_device.type in gpu_dma_types:
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dma_cntrl.requestToDir = MessageBuffer(buffer_size=0)
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dma_cntrl.requestToDir.out_port = self.network_gpu.in_port
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dma_cntrl.responseFromDir = MessageBuffer(buffer_size=0)
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dma_cntrl.responseFromDir.in_port = self.network_gpu.out_port
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dma_cntrl.mandatoryQueue = MessageBuffer(buffer_size = 0)
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gpu_dma_ctrls.append(dma_cntrl)
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else:
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dma_cntrl.requestToDir = MessageBuffer(buffer_size=0)
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dma_cntrl.requestToDir.out_port = self.network_cpu.in_port
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dma_cntrl.responseFromDir = MessageBuffer(buffer_size=0)
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dma_cntrl.responseFromDir.in_port = self.network_cpu.out_port
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dma_cntrl.mandatoryQueue = MessageBuffer(buffer_size = 0)
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cpu_dma_ctrls.append(dma_cntrl)
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dma_cntrls.append(dma_cntrl)
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system.dma_cntrls = dma_cntrls
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# Collect CPU and GPU controllers into seperate lists
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cpu_cntrls = cpu_dir_nodes + cp_cntrl_nodes + cpu_dma_ctrls
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gpu_cntrls = tcp_cntrl_nodes + sqc_cntrl_nodes + \
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scalar_cntrl_nodes + tcc_cntrl_nodes + gpu_dma_ctrls + \
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gpu_dir_nodes
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# Setup number of vnets
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self.number_of_virtual_networks = 11
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self.network_cpu.number_of_virtual_networks = 11
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self.network_gpu.number_of_virtual_networks = 11
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# Set up the disjoint topology
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self.network_cpu.connectCPU(options, cpu_cntrls)
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self.network_gpu.connectGPU(options, gpu_cntrls)
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# Create port proxy for connecting system port. System port is used
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# for loading from outside guest, e.g., binaries like vmlinux.
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system.sys_port_proxy = RubyPortProxy(ruby_system = self)
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system.sys_port_proxy.pio_request_port = piobus.cpu_side_ports
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system.system_port = system.sys_port_proxy.in_ports
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# Only CPU sequencers connect to PIO bus. This acts as the "default"
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# destination for unknown address ranges. PCIe requests fall under
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# this category.
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for i in range(len(cp_sequencers)):
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cp_sequencers[i].pio_request_port = piobus.cpu_side_ports
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cp_sequencers[i].mem_request_port = piobus.cpu_side_ports
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# The CorePairs in MOESI_AMD_Base round up when constructing
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# sequencers, but if the CPU does not exit there would be no
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# sequencer to send a range change, leading to assert.
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if i < options.num_cpus:
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cp_sequencers[i].pio_response_port = piobus.mem_side_ports
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# Setup ruby port. Both CPU and GPU are actually connected here.
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all_sequencers = cp_sequencers + tcp_sequencers + \
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sqc_sequencers + scalar_sequencers
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self._cpu_ports = all_sequencers
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self.num_of_sequencers = len(all_sequencers)
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