Ron Dreslinski dd18ffe51d Fix a memory leak in the memtester ...

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extra : convert_revision : 93062b0f1a3ba7a5210e2f27099f20ae8f66522b

2006-10-12 13:43:12 -04:00

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arch

Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing)

2006-10-08 10:53:24 -07:00

base

Fix problems with unCacheable addresses in timing-coherence

2006-10-12 13:33:21 -04:00

cpu

Fix a memory leak in the memtester

2006-10-12 13:43:12 -04:00

dev

post checkpoint restoration the bus ranges need to be re-initialized for ALL pci devs, not just ide.

2006-10-08 23:18:19 -04:00

doxygen

Fix up doxygen.

2006-08-14 19:25:07 -04:00

kern

Allocate new thread stacks and shared mem region via Process page table

2006-10-08 04:29:40 -04:00

mem

Fix problems with unCacheable addresses in timing-coherence

2006-10-12 13:33:21 -04:00

python

More cache fixes. Atomic coherence now works as well.

2006-10-11 18:28:33 -04:00

sim

Merge zizzer:/bk/newmem

2006-10-06 21:46:04 -04:00

unittest

Merge iceaxe.:/Volumes/work/research/m5/head

2006-06-11 22:01:34 -04:00

Doxyfile

Fix up doxygen.

2006-08-14 19:25:07 -04:00

SConscript

Two minor fixes.

2006-10-10 01:49:46 -04:00