952c4f5eea
Change-Id: I3576df2b7bee1289db60bb6072bd9c90038ca8ce Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
132 lines
4.0 KiB
C++
132 lines
4.0 KiB
C++
/*
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* Copyright (c) 2023 Arm Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2006-2009 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CPU_NATIVETRACE_HH__
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#define __CPU_NATIVETRACE_HH__
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#include <unistd.h>
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#include <cerrno>
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#include "base/socket.hh"
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#include "base/trace.hh"
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#include "base/types.hh"
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#include "cpu/exetrace.hh"
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#include "cpu/static_inst.hh"
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namespace gem5
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{
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class ThreadContext;
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namespace trace {
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class NativeTrace;
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class NativeTraceRecord : public ExeTracerRecord
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{
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public:
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NativeTraceRecord(NativeTrace *_parent,
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Tick _when, ThreadContext *_thread,
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const StaticInstPtr _staticInst, const PCStateBase &_pc,
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const StaticInstPtr _macroStaticInst=nullptr);
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void dump();
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private:
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NativeTrace *parent;
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};
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class NativeTrace : public ExeTracer
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{
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protected:
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int fd;
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ListenSocketPtr native_listener;
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public:
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NativeTrace(const Params &p);
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virtual ~NativeTrace() {}
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NativeTraceRecord *
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getInstRecord(Tick when, ThreadContext *tc,
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const StaticInstPtr staticInst, const PCStateBase &pc,
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const StaticInstPtr macroStaticInst=nullptr) override
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{
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return new NativeTraceRecord(this, when, tc,
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staticInst, pc, macroStaticInst);
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}
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template<class T>
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bool
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checkReg(const char * regName, T &val, T &realVal)
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{
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if (val != realVal)
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{
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DPRINTFN("Register %s should be %#x but is %#x.\n",
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regName, realVal, val);
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return false;
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}
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return true;
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}
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void
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read(void *ptr, size_t size)
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{
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size_t soFar = 0;
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while (soFar < size) {
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ssize_t res = ::read(fd, (uint8_t *)ptr + soFar, size - soFar);
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if (res < 0)
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panic("Read call failed! %s\n", strerror(errno));
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else
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soFar += res;
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}
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}
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virtual void
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check(NativeTraceRecord *record) = 0;
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};
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} // namespace trace
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} // namespace gem5
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#endif // __CPU_NATIVETRACE_HH__
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