5efe4d4a3a
Change-Id: I352e12d4742f0771859bdbf9634ac87e2c153427 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49764 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
94 lines
3.5 KiB
C++
94 lines
3.5 KiB
C++
/*
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* Copyright (c) 2020 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __ARCH_ARM_HTM_HH__
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#define __ARCH_ARM_HTM_HH__
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/**
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* @file
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*
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* ISA-specific types for hardware transactional memory.
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*/
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#include "arch/arm/regs/int.hh"
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#include "arch/arm/regs/vec.hh"
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#include "arch/generic/htm.hh"
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#include "base/types.hh"
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namespace gem5
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{
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namespace ArmISA
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{
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class HTMCheckpoint : public BaseHTMCheckpoint
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{
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public:
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HTMCheckpoint()
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: BaseHTMCheckpoint()
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{}
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const static int MAX_HTM_DEPTH = 255;
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void reset() override;
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void save(ThreadContext *tc) override;
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void restore(ThreadContext *tc, HtmFailureFaultCause cause) override;
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void destinationRegister(RegIndex dest) { rt = dest; }
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void cancelReason(uint16_t reason) { tcreason = reason; }
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private:
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uint8_t rt; // TSTART destination register
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Addr nPc; // Fallback instruction address
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std::array<RegVal, int_reg::NumArchRegs> x; // General purpose registers
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std::array<VecRegContainer, NumVecRegs> z; // Vector registers
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std::array<VecPredRegContainer, NumVecRegs> p; // Predicate registers
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Addr sp; // Stack Pointer at current EL
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uint16_t tcreason; // TCANCEL reason
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uint32_t fpcr; // Floating-point Control Register
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uint32_t fpsr; // Floating-point Status Register
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uint32_t iccPmrEl1; // Interrupt Controller Interrupt Priority Mask
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uint8_t nzcv; // Condition flags
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uint8_t daif;
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PCState pcstateckpt;
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};
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} // namespace ArmISA
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} // namespace gem5
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#endif
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