dab7c78eca
Add NVM interface to memory controller. This can be used with or instead of the existing DRAM interface. Therefore, a single controller can interface to either DRAM or NVM, or both. Specifically, a memory channel can be configured as: - Memory controller interfacing to DRAM only - Memory controller interfacing to NVM only - Memory controller interfacing to both DRAM and NVM How data is placed or migrated between media types is outside of the scope of this change. The NVM interface incorporates new static delay parameters for read and write completion. The interface defines a 2 stage read to manage non-deterministic read delays while enabling deterministic data transfer, similar to NVDIMM-P. The NVM interface also includes parameters to define read and write buffers on the media side (on-DIMM). These are utilized to quickly offload commands and write data, mitigating the effects of lower latency and bandwidth media characteristics. Change-Id: I6b22ddb495877f88d161f0bd74ade32cc8fdcbcc Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29027 Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Reviewed-by: Wendy Elsasser <wendy.elsasser@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Jason Lowe-Power <power.jg@gmail.com>
67 lines
2.7 KiB
Python
67 lines
2.7 KiB
Python
# -*- mode:python -*-
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# Copyright (c) 2012, 2017-2020 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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Import('*')
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Source('base.cc')
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Source('base_gen.cc')
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Source('dram_gen.cc')
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Source('dram_rot_gen.cc')
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Source('exit_gen.cc')
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Source('hybrid_gen.cc')
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Source('idle_gen.cc')
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Source('linear_gen.cc')
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Source('nvm_gen.cc')
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Source('random_gen.cc')
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Source('stream_gen.cc')
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DebugFlag('TrafficGen')
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SimObject('BaseTrafficGen.py')
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if env['USE_PYTHON']:
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Source('pygen.cc', add_tags='python')
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SimObject('PyTrafficGen.py')
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# Only build the traffic generator if we have support for protobuf as the
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# tracing relies on it
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if env['HAVE_PROTOBUF']:
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SimObject('TrafficGen.py')
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Source('trace_gen.cc')
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Source('traffic_gen.cc')
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