dab7c78eca
Add NVM interface to memory controller. This can be used with or instead of the existing DRAM interface. Therefore, a single controller can interface to either DRAM or NVM, or both. Specifically, a memory channel can be configured as: - Memory controller interfacing to DRAM only - Memory controller interfacing to NVM only - Memory controller interfacing to both DRAM and NVM How data is placed or migrated between media types is outside of the scope of this change. The NVM interface incorporates new static delay parameters for read and write completion. The interface defines a 2 stage read to manage non-deterministic read delays while enabling deterministic data transfer, similar to NVDIMM-P. The NVM interface also includes parameters to define read and write buffers on the media side (on-DIMM). These are utilized to quickly offload commands and write data, mitigating the effects of lower latency and bandwidth media characteristics. Change-Id: I6b22ddb495877f88d161f0bd74ade32cc8fdcbcc Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29027 Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Reviewed-by: Wendy Elsasser <wendy.elsasser@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Jason Lowe-Power <power.jg@gmail.com>
276 lines
11 KiB
Python
276 lines
11 KiB
Python
# Copyright (c) 2012, 2017-2018 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Copyright (c) 2006-2007 The Regents of The University of Michigan
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# Copyright (c) 2009 Advanced Micro Devices, Inc.
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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from __future__ import print_function
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import math
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import m5
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from m5.objects import *
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from m5.defines import buildEnv
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from m5.util import addToPath, fatal
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addToPath('../')
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from common import ObjectList
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from common import MemConfig
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from common import FileSystemConfig
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from topologies import *
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from network import Network
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def define_options(parser):
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# By default, ruby uses the simple timing cpu
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parser.set_defaults(cpu_type="TimingSimpleCPU")
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parser.add_option("--ruby-clock", action="store", type="string",
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default='2GHz',
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help="Clock for blocks running at Ruby system's speed")
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parser.add_option("--access-backing-store", action="store_true", default=False,
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help="Should ruby maintain a second copy of memory")
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# Options related to cache structure
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parser.add_option("--ports", action="store", type="int", default=4,
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help="used of transitions per cycle which is a proxy \
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for the number of ports.")
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# network options are in network/Network.py
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# ruby mapping options
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parser.add_option("--numa-high-bit", type="int", default=0,
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help="high order address bit to use for numa mapping. " \
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"0 = highest bit, not specified = lowest bit")
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parser.add_option("--interleaving-bits", type="int", default=0,
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help="number of bits to specify interleaving " \
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"in directory, memory controllers and caches. "
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"0 = not specified")
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parser.add_option("--xor-low-bit", type="int", default=20,
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help="hashing bit for channel selection" \
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"see MemConfig for explanation of the default"\
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"parameter. If set to 0, xor_high_bit is also"\
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"set to 0.")
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parser.add_option("--recycle-latency", type="int", default=10,
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help="Recycle latency for ruby controller input buffers")
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protocol = buildEnv['PROTOCOL']
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exec("from . import %s" % protocol)
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eval("%s.define_options(parser)" % protocol)
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Network.define_options(parser)
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def setup_memory_controllers(system, ruby, dir_cntrls, options):
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if (options.numa_high_bit):
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block_size_bits = options.numa_high_bit + 1 - \
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int(math.log(options.num_dirs, 2))
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ruby.block_size_bytes = 2 ** (block_size_bits)
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else:
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ruby.block_size_bytes = options.cacheline_size
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ruby.memory_size_bits = 48
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index = 0
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mem_ctrls = []
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crossbars = []
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if options.numa_high_bit:
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dir_bits = int(math.log(options.num_dirs, 2))
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intlv_size = 2 ** (options.numa_high_bit - dir_bits + 1)
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else:
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# if the numa_bit is not specified, set the directory bits as the
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# lowest bits above the block offset bits
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intlv_size = options.cacheline_size
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# Sets bits to be used for interleaving. Creates memory controllers
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# attached to a directory controller. A separate controller is created
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# for each address range as the abstract memory can handle only one
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# contiguous address range as of now.
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for dir_cntrl in dir_cntrls:
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crossbar = None
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if len(system.mem_ranges) > 1:
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crossbar = IOXBar()
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crossbars.append(crossbar)
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dir_cntrl.memory = crossbar.slave
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dir_ranges = []
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for r in system.mem_ranges:
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mem_type = ObjectList.mem_list.get(options.mem_type)
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dram_intf = MemConfig.create_mem_intf(mem_type, r, index,
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options.num_dirs, int(math.log(options.num_dirs, 2)),
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intlv_size, options.xor_low_bit)
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mem_ctrl = m5.objects.DRAMCtrl(dram = dram_intf)
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if options.access_backing_store:
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mem_ctrl.kvm_map=False
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mem_ctrls.append(mem_ctrl)
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dir_ranges.append(mem_ctrl.dram.range)
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if crossbar != None:
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mem_ctrl.port = crossbar.master
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else:
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mem_ctrl.port = dir_cntrl.memory
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# Enable low-power DRAM states if option is set
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if issubclass(mem_type, DRAMInterface):
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mem_ctrl.dram.enable_dram_powerdown = \
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options.enable_dram_powerdown
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index += 1
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dir_cntrl.addr_ranges = dir_ranges
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system.mem_ctrls = mem_ctrls
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if len(crossbars) > 0:
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ruby.crossbars = crossbars
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def create_topology(controllers, options):
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""" Called from create_system in configs/ruby/<protocol>.py
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Must return an object which is a subclass of BaseTopology
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found in configs/topologies/BaseTopology.py
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This is a wrapper for the legacy topologies.
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"""
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exec("import topologies.%s as Topo" % options.topology)
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topology = eval("Topo.%s(controllers)" % options.topology)
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return topology
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def create_system(options, full_system, system, piobus = None, dma_ports = [],
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bootmem=None):
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system.ruby = RubySystem()
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ruby = system.ruby
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# Generate pseudo filesystem
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FileSystemConfig.config_filesystem(system, options)
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# Create the network object
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(network, IntLinkClass, ExtLinkClass, RouterClass, InterfaceClass) = \
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Network.create_network(options, ruby)
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ruby.network = network
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protocol = buildEnv['PROTOCOL']
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exec("from . import %s" % protocol)
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try:
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(cpu_sequencers, dir_cntrls, topology) = \
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eval("%s.create_system(options, full_system, system, dma_ports,\
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bootmem, ruby)"
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% protocol)
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except:
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print("Error: could not create sytem for ruby protocol %s" % protocol)
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raise
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# Create the network topology
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topology.makeTopology(options, network, IntLinkClass, ExtLinkClass,
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RouterClass)
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# Register the topology elements with faux filesystem (SE mode only)
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if not full_system:
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topology.registerTopology(options)
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# Initialize network based on topology
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Network.init_network(options, network, InterfaceClass)
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# Create a port proxy for connecting the system port. This is
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# independent of the protocol and kept in the protocol-agnostic
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# part (i.e. here).
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sys_port_proxy = RubyPortProxy(ruby_system = ruby)
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if piobus is not None:
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sys_port_proxy.pio_master_port = piobus.slave
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# Give the system port proxy a SimObject parent without creating a
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# full-fledged controller
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system.sys_port_proxy = sys_port_proxy
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# Connect the system port for loading of binaries etc
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system.system_port = system.sys_port_proxy.slave
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setup_memory_controllers(system, ruby, dir_cntrls, options)
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# Connect the cpu sequencers and the piobus
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if piobus != None:
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for cpu_seq in cpu_sequencers:
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cpu_seq.pio_master_port = piobus.slave
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cpu_seq.mem_master_port = piobus.slave
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if buildEnv['TARGET_ISA'] == "x86":
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cpu_seq.pio_slave_port = piobus.master
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ruby.number_of_virtual_networks = ruby.network.number_of_virtual_networks
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ruby._cpu_ports = cpu_sequencers
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ruby.num_of_sequencers = len(cpu_sequencers)
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# Create a backing copy of physical memory in case required
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if options.access_backing_store:
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ruby.access_backing_store = True
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ruby.phys_mem = SimpleMemory(range=system.mem_ranges[0],
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in_addr_map=False)
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def create_directories(options, bootmem, ruby_system, system):
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dir_cntrl_nodes = []
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for i in range(options.num_dirs):
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dir_cntrl = Directory_Controller()
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dir_cntrl.version = i
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dir_cntrl.directory = RubyDirectoryMemory()
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dir_cntrl.ruby_system = ruby_system
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exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
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dir_cntrl_nodes.append(dir_cntrl)
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if bootmem is not None:
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rom_dir_cntrl = Directory_Controller()
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rom_dir_cntrl.directory = RubyDirectoryMemory()
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rom_dir_cntrl.ruby_system = ruby_system
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rom_dir_cntrl.version = i + 1
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rom_dir_cntrl.memory = bootmem.port
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rom_dir_cntrl.addr_ranges = bootmem.range
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return (dir_cntrl_nodes, rom_dir_cntrl)
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return (dir_cntrl_nodes, None)
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def send_evicts(options):
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# currently, 2 scenarios warrant forwarding evictions to the CPU:
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# 1. The O3 model must keep the LSQ coherent with the caches
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# 2. The x86 mwait instruction is built on top of coherence invalidations
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# 3. The local exclusive monitor in ARM systems
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if options.cpu_type == "DerivO3CPU" or \
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buildEnv['TARGET_ISA'] in ('x86', 'arm'):
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return True
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return False
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