fe8eda9c4e
The ISA parser now emits the code required to access matrix registers. In the case where a register is both a source and a destination, the ISA parser generates appropriate code to make sure that the contents of the source is copied to the destination. This is required for the O3 CPU which treats these as two different physical registers, and hence data is lost if not explicitly preserved. Jira Issue: https://gem5.atlassian.net/browse/GEM5-1289 Change-Id: I8796bd1ea55b5edf5fb8ab92ef1a6060ccc58fa1 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64338 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
116 lines
5.6 KiB
C++
116 lines
5.6 KiB
C++
/*
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* Copyright (c) 2010, 2017-2018, 2022 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CPU__OP_CLASS_HH__
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#define __CPU__OP_CLASS_HH__
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#include "enums/OpClass.hh"
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namespace gem5
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{
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/*
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* Do a bunch of wonky stuff to maintain backward compatability so I
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* don't have to change code in a zillion places.
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*/
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using enums::OpClass;
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using enums::No_OpClass;
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static const OpClass IntAluOp = enums::IntAlu;
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static const OpClass IntMultOp = enums::IntMult;
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static const OpClass IntDivOp = enums::IntDiv;
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static const OpClass FloatAddOp = enums::FloatAdd;
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static const OpClass FloatCmpOp = enums::FloatCmp;
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static const OpClass FloatCvtOp = enums::FloatCvt;
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static const OpClass FloatMultOp = enums::FloatMult;
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static const OpClass FloatMultAccOp = enums::FloatMultAcc;
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static const OpClass FloatDivOp = enums::FloatDiv;
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static const OpClass FloatMiscOp = enums::FloatMisc;
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static const OpClass FloatSqrtOp = enums::FloatSqrt;
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static const OpClass SimdAddOp = enums::SimdAdd;
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static const OpClass SimdAddAccOp = enums::SimdAddAcc;
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static const OpClass SimdAluOp = enums::SimdAlu;
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static const OpClass SimdCmpOp = enums::SimdCmp;
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static const OpClass SimdCvtOp = enums::SimdCvt;
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static const OpClass SimdMiscOp = enums::SimdMisc;
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static const OpClass SimdMultOp = enums::SimdMult;
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static const OpClass SimdMultAccOp = enums::SimdMultAcc;
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static const OpClass SimdShiftOp = enums::SimdShift;
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static const OpClass SimdShiftAccOp = enums::SimdShiftAcc;
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static const OpClass SimdDivOp = enums::SimdDiv;
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static const OpClass SimdSqrtOp = enums::SimdSqrt;
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static const OpClass SimdReduceAddOp = enums::SimdReduceAdd;
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static const OpClass SimdReduceAluOp = enums::SimdReduceAlu;
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static const OpClass SimdReduceCmpOp = enums::SimdReduceCmp;
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static const OpClass SimdFloatAddOp = enums::SimdFloatAdd;
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static const OpClass SimdFloatAluOp = enums::SimdFloatAlu;
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static const OpClass SimdFloatCmpOp = enums::SimdFloatCmp;
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static const OpClass SimdFloatCvtOp = enums::SimdFloatCvt;
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static const OpClass SimdFloatDivOp = enums::SimdFloatDiv;
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static const OpClass SimdFloatMiscOp = enums::SimdFloatMisc;
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static const OpClass SimdFloatMultOp = enums::SimdFloatMult;
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static const OpClass SimdFloatMultAccOp = enums::SimdFloatMultAcc;
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static const OpClass SimdFloatSqrtOp = enums::SimdFloatSqrt;
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static const OpClass SimdFloatReduceCmpOp = enums::SimdFloatReduceCmp;
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static const OpClass SimdFloatReduceAddOp = enums::SimdFloatReduceAdd;
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static const OpClass SimdAesOp = enums::SimdAes;
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static const OpClass SimdAesMixOp = enums::SimdAesMix;
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static const OpClass SimdSha1HashOp = enums::SimdSha1Hash;
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static const OpClass SimdSha1Hash2Op = enums::SimdSha1Hash2;
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static const OpClass SimdSha256HashOp = enums::SimdSha256Hash;
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static const OpClass SimdSha256Hash2Op = enums::SimdSha256Hash2;
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static const OpClass SimdShaSigma2Op = enums::SimdShaSigma2;
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static const OpClass SimdShaSigma3Op = enums::SimdShaSigma3;
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static const OpClass SimdPredAluOp = enums::SimdPredAlu;
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static const OpClass MatrixOp = enums::Matrix;
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static const OpClass MatrixMovOp = enums::MatrixMov;
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static const OpClass MatrixOPOp = enums::MatrixOP;
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static const OpClass MemReadOp = enums::MemRead;
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static const OpClass MemWriteOp = enums::MemWrite;
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static const OpClass FloatMemReadOp = enums::FloatMemRead;
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static const OpClass FloatMemWriteOp = enums::FloatMemWrite;
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static const OpClass IprAccessOp = enums::IprAccess;
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static const OpClass InstPrefetchOp = enums::InstPrefetch;
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static const OpClass Num_OpClasses = enums::Num_OpClass;
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} // namespace gem5
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#endif // __CPU__OP_CLASS_HH__
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