Ali Saidi d907d0ec72 Cache: Fix an issue with LRU when bonus block is used to complete transaction. ...

The block is never inserted because it's the one extra block in the cache, but
it can be invalidated twice in a row. In that case the block doesn't have a
new master id (beacuse it was never inserted), however it is valid and
the accounting goes wrong at that point.

2012-03-01 17:26:31 -06:00

..

prefetch

mem: Add a master ID to each request object.

2012-02-12 16:07:38 -06:00

tags

mem: fix cache stats to use request ids correctly

2012-02-12 16:07:39 -06:00

base.cc

MEM: Simplify cache ports preparing for master/slave split

2012-02-24 11:52:49 -05:00

base.hh

MEM: Simplify cache ports preparing for master/slave split

2012-02-24 11:52:49 -05:00

BaseCache.py

MEM: Introduce the master/slave port roles in the Python classes

2012-02-13 06:43:09 -05:00

blk.cc

Fix #include lines for renamed cache files.

2008-02-10 14:45:25 -08:00

blk.hh

mem: fix cache stats to use request ids correctly

2012-02-12 16:07:39 -06:00

builder.cc

prefetcher: Make prefetcher a sim object instead of it being a parameter on cache

2012-02-12 16:07:38 -06:00

cache_impl.hh

Cache: Fix an issue with LRU when bonus block is used to complete transaction.

2012-03-01 17:26:31 -06:00

cache.cc

remove the totally obsolete split cache

2008-10-23 16:11:28 -04:00

cache.hh

MEM: Simplify cache ports preparing for master/slave split

2012-02-24 11:52:49 -05:00

mshr_queue.cc

cache: coherence protocol enhancements & bug fixes

2010-09-09 14:40:18 -04:00

mshr_queue.hh

includes: sort all includes

2011-04-15 10:44:06 -07:00

mshr.cc

trace: reimplement the DTRACE function so it doesn't use a vector

2011-04-15 10:44:32 -07:00

mshr.hh

Replace curTick global variable with accessor functions.

2011-01-07 21:50:29 -08:00

SConscript

scons: rename TraceFlags to DebugFlags

2011-06-02 17:36:21 -07:00