Files
gem5/src
Giacomo Travaglini d8dd86d4ce arch: Fix VecElem Operand generation in ISA parser
Fixes include:

* Change of reg_class: VecElemClass in lieau of non-existing
  VectorElemClass.
* Removal of unused regId in operand constructor
* makeRead and makeWrite are using VecElem (which is a typedef
  of uint32_t) as a source/destination type, regardless of the real
  operand type (which is specified by ctype)

Change-Id: I4588e1120e1fc8fdb68b2b2f05d5e3692c55b2e8
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15602
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
2019-01-25 12:55:27 +00:00
..
2019-01-24 14:12:35 +00:00
2018-04-20 15:59:35 +00:00
2019-01-22 02:14:47 +00:00
2018-07-10 16:41:40 +00:00