28e9641c2c
Fix fixPacket assert function.
Stop timing port from forwarding the request if a response was found in its queue on a read.
src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
src/python/m5/objects/MemTest.py:
Add parameter to configure what percentage of mem accesses are functional
src/mem/cache/base_cache.cc:
src/mem/cache/cache_impl.hh:
Use fix Packet function
src/mem/packet.cc:
Fix an assert that was checking the wrong thing
src/mem/tport.cc:
Properly detect if we need to do the access to the functional device
--HG--
extra : convert_revision : 447cc1a9a65ddd2a41e937fb09dc0e7c74e9c75e
25 lines
1.0 KiB
Python
25 lines
1.0 KiB
Python
from m5.SimObject import SimObject
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from m5.params import *
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from m5.proxy import *
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from m5 import build_env
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class MemTest(SimObject):
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type = 'MemTest'
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max_loads = Param.Counter("number of loads to execute")
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atomic = Param.Bool(False, "Execute tester in atomic mode? (or timing)\n")
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memory_size = Param.Int(65536, "memory size")
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percent_dest_unaligned = Param.Percent(50,
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"percent of copy dest address that are unaligned")
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percent_reads = Param.Percent(65, "target read percentage")
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percent_source_unaligned = Param.Percent(50,
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"percent of copy source address that are unaligned")
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percent_functional = Param.Percent(50, "percent of access that are functional")
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percent_uncacheable = Param.Percent(10,
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"target uncacheable percentage")
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progress_interval = Param.Counter(1000000,
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"progress report interval (in accesses)")
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trace_addr = Param.Addr(0, "address to trace")
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test = Port("Port to the memory system to test")
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functional = Port("Port to the functional memory used for verification")
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