24da30e317
This basically means changing all #include statements and changing autogenerated code so that it generates the correct paths. Because slicc generates #includes, I had to hard code the include paths to mem/protocol.
366 lines
14 KiB
C++
366 lines
14 KiB
C++
/*
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* Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <stdio.h>
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#include <math.h>
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#include "mem/ruby/network/orion/power_ll.hh"
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#include "mem/ruby/network/orion/power_crossbar.hh"
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#include "mem/ruby/network/orion/parm_technology.hh"
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#include "mem/ruby/network/orion/SIM_port.hh"
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#include "mem/ruby/network/orion/power_static.hh"
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#include "mem/ruby/network/orion/power_utils.hh"
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/*-------------------- CROSSBAR power model -------------------*/
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static double crossbar_in_cap(double wire_cap, unsigned n_out, int connect_type, int trans_type, double *Nsize)
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{
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double Ctotal = 0, Ctrans = 0, psize, nsize, Cdriver = 0;
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/* part 1: wire cap */
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Ctotal += wire_cap;
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//printf("CROSSBAR_INTERNAL: input wire cap = %g\n", wire_cap);
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/* part 2: drain cap of transmission gate or gate cap of tri-state gate */
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if (connect_type == TRANS_GATE) {
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/* FIXME: resizing strategy */
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nsize = Nsize ? *Nsize : Wmemcellr;
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psize = nsize * Wdecinvp / Wdecinvn;
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Ctrans = SIM_power_draincap(nsize, NCH, 1);
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if (trans_type == NP_GATE)
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Ctrans += SIM_power_draincap(psize, PCH, 1);
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}
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else if (connect_type == TRISTATE_GATE) {
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Ctrans = SIM_power_gatecap(Woutdrvnandn + Woutdrvnandp, 0) +
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SIM_power_gatecap(Woutdrvnorn + Woutdrvnorp, 0);
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}
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else {/* some error handler */}
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//printf("CROSSBAR_INTERNAL: input connector cap = %g\n", (n_out * Ctrans));
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Ctotal += n_out * Ctrans;
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/* part 3: input driver */
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/* FIXME: how to specify timing? */
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psize = SIM_power_driver_size(Ctotal, Period / 3);
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nsize = psize * Wdecinvn / Wdecinvp;
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Cdriver = SIM_power_draincap(nsize, NCH, 1) + SIM_power_draincap(psize, PCH, 1) +
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SIM_power_gatecap(nsize + psize, 0);
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//printf("CROSSBAR_INTERNAL: input driver cap = %g\n", Cdriver);
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Ctotal += Cdriver;
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return Ctotal / 2;
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}
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static double crossbar_out_cap(double length, unsigned n_in, int connect_type, int trans_type, double *Nsize)
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{
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double Ctotal = 0, Cwire = 0, Ctrans = 0, Cdriver = 0, psize, nsize;
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/* part 1: wire cap */
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Cwire += CC3metal * length;
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//printf("CROSSBAR_INTERNAL: output wire cap = %g\n", Cwire);
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Ctotal += Cwire;
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/* part 2: drain cap of transmission gate or tri-state gate */
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if (connect_type == TRANS_GATE) {
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/* FIXME: resizing strategy */
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if (Nsize) {
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/* FIXME: how to specify timing? */
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psize = SIM_power_driver_size(Ctotal, Period / 3);
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*Nsize = nsize = psize * Wdecinvn / Wdecinvp;
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}
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else {
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nsize = Wmemcellr;
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psize = nsize * Wdecinvp / Wdecinvn;
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}
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Ctrans = SIM_power_draincap(nsize, NCH, 1);
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if (trans_type == NP_GATE)
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Ctrans += SIM_power_draincap(psize, PCH, 1);
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}
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else if (connect_type == TRISTATE_GATE) {
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Ctrans = SIM_power_draincap(Woutdrivern, NCH, 1) + SIM_power_draincap(Woutdriverp, PCH, 1);
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}
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else {/* some error handler */}
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//printf("CROSSBAR_INTERNAL: output connector cap = %g\n", (n_in * Ctrans));
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Ctotal += n_in * Ctrans;
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/* part 3: output driver */
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Cdriver += SIM_power_draincap(Woutdrivern, NCH, 1) + SIM_power_draincap(Woutdriverp, PCH, 1) +
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SIM_power_gatecap(Woutdrivern + Woutdriverp, 0);
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//printf("CROSSBAR_INTERNAL: output driver cap = %g\n", Cdriver);
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Ctotal += Cdriver;
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return Ctotal / 2;
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}
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/* cut-through crossbar only supports 4x4 now */
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static double crossbar_io_cap(double length)
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{
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double Ctotal = 0, psize, nsize;
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/* part 1: wire cap */
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Ctotal += CC3metal * length;
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/* part 2: gate cap of tri-state gate */
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Ctotal += 2 * (SIM_power_gatecap(Woutdrvnandn + Woutdrvnandp, 0) +
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SIM_power_gatecap(Woutdrvnorn + Woutdrvnorp, 0));
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/* part 3: drain cap of tri-state gate */
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Ctotal += 2 * (SIM_power_draincap(Woutdrivern, NCH, 1) + SIM_power_draincap(Woutdriverp, PCH, 1));
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/* part 4: input driver */
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/* FIXME: how to specify timing? */
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psize = SIM_power_driver_size(Ctotal, Period * 0.8);
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nsize = psize * Wdecinvn / Wdecinvp;
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Ctotal += SIM_power_draincap(nsize, NCH, 1) + SIM_power_draincap(psize, PCH, 1) +
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SIM_power_gatecap(nsize + psize, 0);
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/* part 5: output driver */
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Ctotal += SIM_power_draincap(Woutdrivern, NCH, 1) + SIM_power_draincap(Woutdriverp, PCH, 1) +
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SIM_power_gatecap(Woutdrivern + Woutdriverp, 0);
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/* HACK HACK HACK */
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/* this HACK is to count a 1:4 mux and a 4:1 mux, so we have a 5x5 crossbar */
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return Ctotal / 2 * 1.32;
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}
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static double crossbar_int_cap(unsigned degree, int connect_type, int trans_type)
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{
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double Ctotal = 0, Ctrans;
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if (connect_type == TRANS_GATE) {
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/* part 1: drain cap of transmission gate */
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/* FIXME: Wmemcellr and resize */
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Ctrans = SIM_power_draincap(Wmemcellr, NCH, 1);
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if (trans_type == NP_GATE)
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Ctrans += SIM_power_draincap(Wmemcellr * Wdecinvp / Wdecinvn, PCH, 1);
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Ctotal += (degree + 1) * Ctrans;
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}
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else if (connect_type == TRISTATE_GATE) {
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/* part 1: drain cap of tri-state gate */
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Ctotal += degree * (SIM_power_draincap(Woutdrivern, NCH, 1) + SIM_power_draincap(Woutdriverp, PCH, 1));
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/* part 2: gate cap of tri-state gate */
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Ctotal += SIM_power_gatecap(Woutdrvnandn + Woutdrvnandp, 0) +
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SIM_power_gatecap(Woutdrvnorn + Woutdrvnorp, 0);
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}
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else {/* some error handler */}
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return Ctotal / 2;
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}
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/* FIXME: segment control signals are not handled yet */
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static double crossbar_ctr_cap(double length, unsigned data_width, int prev_ctr, int next_ctr, unsigned degree, int connect_type, int trans_type)
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{
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double Ctotal = 0, Cgate;
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/* part 1: wire cap */
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Ctotal = Cmetal * length;
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/* part 2: gate cap of transmission gate or tri-state gate */
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if (connect_type == TRANS_GATE) {
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/* FIXME: Wmemcellr and resize */
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Cgate = SIM_power_gatecap(Wmemcellr, 0);
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if (trans_type == NP_GATE)
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Cgate += SIM_power_gatecap(Wmemcellr * Wdecinvp / Wdecinvn, 0);
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}
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else if (connect_type == TRISTATE_GATE) {
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Cgate = SIM_power_gatecap(Woutdrvnandn + Woutdrvnandp, 0) +
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SIM_power_gatecap(Woutdrvnorn + Woutdrvnorp, 0);
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}
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else {/* some error handler */}
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Ctotal += data_width * Cgate;
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/* part 3: inverter */
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if (!(connect_type == TRANS_GATE && trans_type == N_GATE && !prev_ctr))
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/* FIXME: need accurate size, use minimal size for now */
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Ctotal += SIM_power_draincap(Wdecinvn, NCH, 1) + SIM_power_draincap(Wdecinvp, PCH, 1) +
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SIM_power_gatecap(Wdecinvn + Wdecinvp, 0);
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/* part 4: drain cap of previous level control signal */
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if (prev_ctr)
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/* FIXME: need actual size, use decoder data for now */
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Ctotal += degree * SIM_power_draincap(WdecNORn, NCH, 1) + SIM_power_draincap(WdecNORp, PCH, degree);
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/* part 5: gate cap of next level control signal */
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if (next_ctr)
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/* FIXME: need actual size, use decoder data for now */
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Ctotal += SIM_power_gatecap(WdecNORn + WdecNORp, degree * 40 + 20);
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return Ctotal;
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}
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int power_crossbar_init(power_crossbar *crsbar, int model, unsigned n_in, unsigned n_out, unsigned data_width, unsigned degree, int connect_type, int trans_type, double in_len, double out_len, double *req_len)
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{
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double in_length, out_length, ctr_length, Nsize, in_wire_cap, i_leakage;
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if ((crsbar->model = model) && model < CROSSBAR_MAX_MODEL) {
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crsbar->n_in = n_in;
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crsbar->n_out = n_out;
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crsbar->data_width = data_width;
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crsbar->degree = degree;
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crsbar->connect_type = connect_type;
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crsbar->trans_type = trans_type;
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/* redundant field */
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crsbar->mask = HAMM_MASK(data_width);
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crsbar->n_chg_in = crsbar->n_chg_int = crsbar->n_chg_out = crsbar->n_chg_ctr = 0;
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switch (model) {
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case MATRIX_CROSSBAR:
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/* FIXME: need accurate spacing */
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in_length = n_out * data_width * CrsbarCellWidth;
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out_length = n_in * data_width * CrsbarCellHeight;
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if (in_length < in_len) in_length = in_len;
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if (out_length < out_len) out_length = out_len;
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ctr_length = in_length / 2;
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if (req_len) *req_len = in_length;
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in_wire_cap = in_length * CC3metal;
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crsbar->e_chg_out = crossbar_out_cap(out_length, n_in, connect_type, trans_type, &Nsize) * EnergyFactor;
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crsbar->e_chg_in = crossbar_in_cap(in_wire_cap, n_out, connect_type, trans_type, &Nsize) * EnergyFactor;
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/* FIXME: wire length estimation, really reset? */
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/* control signal should reset after transmission is done, so no 1/2 */
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crsbar->e_chg_ctr = crossbar_ctr_cap(ctr_length, data_width, 0, 0, 0, connect_type, trans_type) * EnergyFactor;
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crsbar->e_chg_int = 0;
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/* static power */
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i_leakage = 0;
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/* tri-state buffers */
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i_leakage += ((Woutdrvnandp * (NAND2_TAB[0] + NAND2_TAB[1] + NAND2_TAB[2]) + Woutdrvnandn * NAND2_TAB[3]) / 4 +
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(Woutdrvnorp * NOR2_TAB[0] + Woutdrvnorn * (NOR2_TAB[1] + NOR2_TAB[2] + NOR2_TAB[3])) / 4 +
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Woutdrivern * NMOS_TAB[0] + Woutdriverp * PMOS_TAB[0]) * n_in * n_out * data_width;
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/* input driver */
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i_leakage += (Wdecinvn * NMOS_TAB[0] + Wdecinvp * PMOS_TAB[0]) * n_in * data_width;
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/* output driver */
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i_leakage += (Woutdrivern * NMOS_TAB[0] + Woutdriverp * PMOS_TAB[0]) * n_out * data_width;
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/* control signal inverter */
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i_leakage += (Wdecinvn * NMOS_TAB[0] + Wdecinvp * PMOS_TAB[0]) * n_in * n_out;
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crsbar->i_leakage = i_leakage / PARM_TECH_POINT * 100;
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break;
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case MULTREE_CROSSBAR:
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/* input wire horizontal segment length */
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in_length = n_in * data_width * CrsbarCellWidth * (n_out / 2);
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in_wire_cap = in_length * CCmetal;
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/* input wire vertical segment length */
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in_length = n_in * data_width * (5 * Lamda) * (n_out / 2);
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in_wire_cap += in_length * CC3metal;
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ctr_length = n_in * data_width * CrsbarCellWidth * (n_out / 2) / 2;
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crsbar->e_chg_out = crossbar_out_cap(0, degree, connect_type, trans_type, NULL) * EnergyFactor;
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crsbar->e_chg_in = crossbar_in_cap(in_wire_cap, n_out, connect_type, trans_type, NULL) * EnergyFactor;
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crsbar->e_chg_int = crossbar_int_cap(degree, connect_type, trans_type) * EnergyFactor;
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/* redundant field */
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crsbar->depth = (unsigned)ceil(log(n_in) / log(degree));
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/* control signal should reset after transmission is done, so no 1/2 */
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if (crsbar->depth == 1)
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/* only one level of control signal */
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crsbar->e_chg_ctr = crossbar_ctr_cap(ctr_length, data_width, 0, 0, degree, connect_type, trans_type) * EnergyFactor;
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else {
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/* first level and last level control signals */
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crsbar->e_chg_ctr = crossbar_ctr_cap(ctr_length, data_width, 0, 1, degree, connect_type, trans_type) * EnergyFactor +
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crossbar_ctr_cap(0, data_width, 1, 0, degree, connect_type, trans_type) * EnergyFactor;
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/* intermediate control signals */
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if (crsbar->depth > 2)
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crsbar->e_chg_ctr += (crsbar->depth - 2) * crossbar_ctr_cap(0, data_width, 1, 1, degree, connect_type, trans_type) * EnergyFactor;
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}
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/* static power */
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i_leakage = 0;
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/* input driver */
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i_leakage += (Wdecinvn * NMOS_TAB[0] + Wdecinvp * PMOS_TAB[0]) * n_in * data_width;
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/* output driver */
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i_leakage += (Woutdrivern * NMOS_TAB[0] + Woutdriverp * PMOS_TAB[0]) * n_out * data_width;
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/* mux */
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i_leakage += (WdecNORp * NOR2_TAB[0] + WdecNORn * (NOR2_TAB[1] + NOR2_TAB[2] + NOR2_TAB[3])) / 4 * (2 * n_in - 1) * n_out * data_width;
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/* control signal inverter */
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i_leakage += (Wdecinvn * NMOS_TAB[0] + Wdecinvp * PMOS_TAB[0]) * n_in * n_out;
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crsbar->i_leakage = i_leakage / PARM_TECH_POINT * 100;
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break;
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default: break;/* some error handler */
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}
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return 0;
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}
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else
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return -1;
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}
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/* FIXME: MULTREE_CROSSBAR record missing */
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int crossbar_record(power_crossbar *xb, int io, unsigned long int new_data, unsigned long int old_data, unsigned new_port, unsigned old_port)
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{
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switch (xb->model) {
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case MATRIX_CROSSBAR:
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if (io) /* input port */
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xb->n_chg_in += SIM_power_Hamming(new_data, old_data, xb->mask);
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else { /* output port */
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xb->n_chg_out += SIM_power_Hamming(new_data, old_data, xb->mask);
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xb->n_chg_ctr += new_port != old_port;
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}
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break;
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case MULTREE_CROSSBAR:
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break;
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default: break;/* some error handler */
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}
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return 0;
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}
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double crossbar_report(power_crossbar *crsbar)
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{
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return (crsbar->n_chg_in * crsbar->e_chg_in + crsbar->n_chg_out * crsbar->e_chg_out +
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crsbar->n_chg_int * crsbar->e_chg_int + crsbar->n_chg_ctr * crsbar->e_chg_ctr);
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}
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/* ---------- crossbar model ---------- */
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