c4793184bd
build directory instead of being inferred from the name
of the build directory.
Options are passed to C++ via config/*.hh files instead of
via the command line. Build option flags are now always
defined to 0 or 1, so checks must use '#if' rather than
'#ifdef'.
SConscript:
MySQL detection moved to SConstruct.
Add config/*.hh files (via ConfigFile builder).
arch/alpha/alpha_memory.cc:
arch/alpha/ev5.cc:
arch/alpha/ev5.hh:
arch/alpha/isa_traits.hh:
base/fast_alloc.hh:
base/statistics.cc:
base/statistics.hh:
base/stats/events.cc:
base/stats/events.hh:
cpu/base.cc:
cpu/base.hh:
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
cpu/exec_context.cc:
cpu/exec_context.hh:
cpu/o3/alpha_cpu.hh:
cpu/o3/alpha_cpu_builder.cc:
cpu/o3/alpha_cpu_impl.hh:
cpu/o3/alpha_dyn_inst.hh:
cpu/o3/alpha_dyn_inst_impl.hh:
cpu/o3/alpha_params.hh:
cpu/o3/commit_impl.hh:
cpu/o3/cpu.cc:
cpu/o3/cpu.hh:
cpu/o3/fetch_impl.hh:
cpu/o3/iew.hh:
cpu/o3/iew_impl.hh:
cpu/o3/regfile.hh:
cpu/o3/rename_impl.hh:
cpu/o3/rob_impl.hh:
cpu/ozone/cpu.hh:
cpu/pc_event.cc:
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
sim/process.cc:
sim/process.hh:
Convert compile flags from def/undef to 0/1.
Set via #include config/*.hh instead of command line.
arch/alpha/isa_desc:
Convert compile flags from def/undef to 0/1.
Set via #include config/*.hh instead of command line.
Revamp fenv.h support... most of the ugliness is hidden
in base/fenv.hh now.
base/mysql.hh:
Fix typo in #ifndef guard.
build/SConstruct:
Build options are set via a build_options file in the
build directory instead of being inferred from the name
of the build directory.
Options are passed to C++ via config/*.hh files instead of
via the command line.
python/SConscript:
Generate m5_build_env directly from scons options
instead of indirectly via CPPDEFINES.
python/m5/convert.py:
Allow '0' and '1' for booleans.
Rewrite toBool to use dict.
base/fenv.hh:
Revamp <fenv.h> support to make it a compile option
(so we can test w/o it even if it's present) and to
make isa_desc cleaner.
--HG--
extra : convert_revision : 8f97dc11185bef5e1865b3269c7341df8525c9ad
163 lines
4.2 KiB
C++
163 lines
4.2 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "cpu/o3/alpha_dyn_inst.hh"
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template <class Impl>
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AlphaDynInst<Impl>::AlphaDynInst(MachInst inst, Addr PC, Addr Pred_PC,
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InstSeqNum seq_num, FullCPU *cpu)
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: BaseDynInst<Impl>(inst, PC, Pred_PC, seq_num, cpu)
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{
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// Make sure to have the renamed register entries set to the same
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// as the normal register entries. It will allow the IQ to work
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// without any modifications.
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for (int i = 0; i < this->staticInst->numDestRegs(); i++)
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{
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_destRegIdx[i] = this->staticInst->destRegIdx(i);
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}
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for (int i = 0; i < this->staticInst->numSrcRegs(); i++)
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{
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_srcRegIdx[i] = this->staticInst->srcRegIdx(i);
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this->_readySrcRegIdx[i] = 0;
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}
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}
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template <class Impl>
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AlphaDynInst<Impl>::AlphaDynInst(StaticInstPtr<AlphaISA> &_staticInst)
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: BaseDynInst<Impl>(_staticInst)
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{
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// Make sure to have the renamed register entries set to the same
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// as the normal register entries. It will allow the IQ to work
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// without any modifications.
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for (int i = 0; i < _staticInst->numDestRegs(); i++)
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{
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_destRegIdx[i] = _staticInst->destRegIdx(i);
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}
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for (int i = 0; i < _staticInst->numSrcRegs(); i++)
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{
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_srcRegIdx[i] = _staticInst->srcRegIdx(i);
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}
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}
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template <class Impl>
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uint64_t
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AlphaDynInst<Impl>::readUniq()
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{
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return this->cpu->readUniq();
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}
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template <class Impl>
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void
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AlphaDynInst<Impl>::setUniq(uint64_t val)
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{
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this->cpu->setUniq(val);
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}
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template <class Impl>
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uint64_t
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AlphaDynInst<Impl>::readFpcr()
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{
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return this->cpu->readFpcr();
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}
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template <class Impl>
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void
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AlphaDynInst<Impl>::setFpcr(uint64_t val)
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{
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this->cpu->setFpcr(val);
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}
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#if FULL_SYSTEM
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template <class Impl>
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uint64_t
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AlphaDynInst<Impl>::readIpr(int idx, Fault &fault)
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{
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return this->cpu->readIpr(idx, fault);
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}
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template <class Impl>
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Fault
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AlphaDynInst<Impl>::setIpr(int idx, uint64_t val)
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{
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return this->cpu->setIpr(idx, val);
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}
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template <class Impl>
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Fault
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AlphaDynInst<Impl>::hwrei()
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{
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return this->cpu->hwrei();
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}
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template <class Impl>
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int
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AlphaDynInst<Impl>::readIntrFlag()
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{
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return this->cpu->readIntrFlag();
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}
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template <class Impl>
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void
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AlphaDynInst<Impl>::setIntrFlag(int val)
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{
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this->cpu->setIntrFlag(val);
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}
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template <class Impl>
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bool
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AlphaDynInst<Impl>::inPalMode()
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{
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return this->cpu->inPalMode();
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}
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template <class Impl>
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void
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AlphaDynInst<Impl>::trap(Fault fault)
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{
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this->cpu->trap(fault);
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}
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template <class Impl>
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bool
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AlphaDynInst<Impl>::simPalCheck(int palFunc)
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{
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return this->cpu->simPalCheck(palFunc);
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}
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#else
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template <class Impl>
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void
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AlphaDynInst<Impl>::syscall()
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{
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this->cpu->syscall(this->threadNumber);
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}
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#endif
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