Andreas Sandberg 550c318490 sim: Move the BaseTLB to src/arch/generic/ ...

The TLB-related code is generally architecture dependent and should
live in the arch directory to signify that.

--HG--
rename : src/sim/BaseTLB.py => src/arch/generic/BaseTLB.py
rename : src/sim/tlb.cc => src/arch/generic/tlb.cc
rename : src/sim/tlb.hh => src/arch/generic/tlb.hh

2015-02-11 10:23:27 -05:00

..

linux

ISA: generic Linux thread info support

2012-11-02 11:32:00 -05:00

BaseTLB.py

sim: Move the BaseTLB to src/arch/generic/

2015-02-11 10:23:27 -05:00

debugfaults.hh

arch: Use const StaticInstPtr references where possible

2014-09-27 09:08:36 -04:00

decode_cache.cc

ISA,CPU: Generalize and split out the components of the decode cache.

2012-05-26 13:45:12 -07:00

decode_cache.hh

ISA,CPU: Generalize and split out the components of the decode cache.

2012-05-26 13:45:12 -07:00

memhelpers.hh

arch: Use shared_ptr for all Faults

2014-10-16 05:49:51 -04:00

mmapped_ipr.cc

mem: Use a flag instead of address bit 63 for generic IPRs

2013-10-15 13:24:35 +02:00

mmapped_ipr.hh

mem: Use a flag instead of address bit 63 for generic IPRs

2013-10-15 13:24:35 +02:00

pseudo_inst.cc

kvm, x86: Adding support for SE mode execution

2014-11-23 18:01:08 -08:00

pseudo_inst.hh

kvm, x86: Adding support for SE mode execution

2014-11-23 18:01:08 -08:00

SConscript

sim: Move the BaseTLB to src/arch/generic/

2015-02-11 10:23:27 -05:00

tlb.cc

sim: Move the BaseTLB to src/arch/generic/

2015-02-11 10:23:27 -05:00

tlb.hh

sim: Move the BaseTLB to src/arch/generic/

2015-02-11 10:23:27 -05:00

types.hh

arm: Fixes based on UBSan and static analysis

2014-11-14 03:53:51 -05:00