4903fe2db1
This is useful in other ISAs to implement FP16 computation. For example, it can be used in the GPU model. The ARM specific misc register is ignored in that case. Change-Id: I339ac0ccd9be4371b0f220ad99068e5e12b3d263
141 lines
6.2 KiB
Python
141 lines
6.2 KiB
Python
# -*- mode:python -*-
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# Copyright (c) 2009, 2012-2013, 2017-2018, 2020 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Copyright (c) 2007-2008 The Florida State University
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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Import('*')
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Source('insts/fplib.cc')
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if env['CONF']['USE_ARM_ISA']:
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env.TagImplies('arm isa', 'gem5 lib')
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# The GTest function does not have a 'tags' parameter. We therefore apply this
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# guard to ensure this test is only built when ARM is compiled.
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#
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# Note: This will need reconfigured for multi-isa. E.g., if this is
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# incorporated: https://gem5-review.googlesource.com/c/public/gem5/+/52491
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if env['CONF']['USE_ARM_ISA']:
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GTest('aapcs64.test', 'aapcs64.test.cc',
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'../../base/debug.cc',
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'../../cpu/reg_class.cc',
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'../../sim/bufval.cc', '../../sim/cur_tick.cc',
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'regs/int.cc')
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GTest('matrix.test', 'matrix.test.cc')
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Source('decoder.cc', tags='arm isa')
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Source('faults.cc', tags='arm isa')
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Source('htm.cc', tags='arm isa')
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Source('insts/branch.cc', tags='arm isa')
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Source('insts/branch64.cc', tags='arm isa')
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Source('insts/data64.cc', tags='arm isa')
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Source('insts/macromem.cc', tags='arm isa')
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Source('insts/mem.cc', tags='arm isa')
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Source('insts/mem64.cc', tags='arm isa')
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Source('insts/misc.cc', tags='arm isa')
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Source('insts/misc64.cc', tags='arm isa')
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Source('insts/pred_inst.cc', tags='arm isa')
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Source('insts/pseudo.cc', tags='arm isa')
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Source('insts/sme.cc', tags='arm isa')
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Source('insts/static_inst.cc', tags='arm isa')
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Source('insts/sve.cc', tags='arm isa')
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Source('insts/sve_mem.cc', tags='arm isa')
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Source('insts/vfp.cc', tags='arm isa')
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Source('insts/crypto.cc', tags='arm isa')
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Source('insts/tme64.cc', tags='arm isa')
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if env['CONF']['PROTOCOL'] == 'MESI_Three_Level_HTM':
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Source('insts/tme64ruby.cc', tags='arm isa')
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else:
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Source('insts/tme64classic.cc', tags='arm isa')
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Source('interrupts.cc', tags='arm isa')
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Source('isa.cc', tags='arm isa')
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Source('isa_device.cc', tags='arm isa')
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Source('linux/process.cc', tags='arm isa')
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Source('linux/se_workload.cc', tags='arm isa')
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Source('linux/fs_workload.cc', tags='arm isa')
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Source('freebsd/fs_workload.cc', tags='arm isa')
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Source('freebsd/se_workload.cc', tags='arm isa')
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Source('fs_workload.cc', tags='arm isa')
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Source('regs/int.cc', tags='arm isa')
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Source('regs/misc.cc', tags='arm isa')
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Source('mmu.cc', tags='arm isa')
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Source('nativetrace.cc', tags='arm isa')
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Source('pagetable.cc', tags='arm isa')
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Source('pauth_helpers.cc', tags='arm isa')
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Source('pmu.cc', tags='arm isa')
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Source('process.cc', tags='arm isa')
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Source('qarma.cc', tags='arm isa')
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Source('remote_gdb.cc', tags='arm isa')
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Source('reg_abi.cc', tags='arm isa')
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Source('semihosting.cc', tags='arm isa')
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Source('system.cc', tags='arm isa')
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Source('table_walker.cc', tags='arm isa')
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Source('self_debug.cc', tags='arm isa')
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Source('stage2_lookup.cc', tags='arm isa')
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Source('tlb.cc', tags='arm isa')
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Source('tlbi_op.cc', tags='arm isa')
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Source('utility.cc', tags='arm isa')
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SimObject('ArmDecoder.py', sim_objects=['ArmDecoder'], tags='arm isa')
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SimObject('ArmFsWorkload.py', sim_objects=[
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'ArmFsWorkload', 'ArmFsLinux', 'ArmFsFreebsd'],
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enums=['ArmMachineType'], tags='arm isa')
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SimObject('ArmInterrupts.py', sim_objects=['ArmInterrupts'], tags='arm isa')
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SimObject('ArmISA.py', sim_objects=['ArmISA'], enums=['DecoderFlavor'],
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tags='arm isa')
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SimObject('ArmMMU.py', sim_objects=['ArmTableWalker', 'ArmMMU'],
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tags='arm isa')
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SimObject('ArmNativeTrace.py', sim_objects=['ArmNativeTrace'], tags='arm isa')
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SimObject('ArmSemihosting.py', sim_objects=['ArmSemihosting'], tags='arm isa')
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SimObject('ArmSeWorkload.py', sim_objects=[
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'ArmSEWorkload', 'ArmEmuLinux', 'ArmEmuFreebsd'], tags='arm isa')
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SimObject('ArmSystem.py', sim_objects=['ArmSystem', 'ArmRelease'],
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enums=['ArmExtension'], tags='arm isa')
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SimObject('ArmTLB.py', sim_objects=['ArmTLB'], enums=['ArmLookupLevel'],
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tags='arm isa')
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SimObject('ArmPMU.py', sim_objects=['ArmPMU'], tags='arm isa')
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SimObject('ArmCPU.py', sim_objects=[], tags='arm isa')
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DebugFlag('Arm', tags='arm isa')
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DebugFlag('ArmTme', 'Transactional Memory Extension', tags='arm isa')
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DebugFlag('Semihosting', tags='arm isa')
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DebugFlag('PMUVerbose', "Performance Monitor", tags='arm isa')
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# Add files generated by the ISA description.
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ISADesc('isa/main.isa', decoder_splits=3, exec_splits=6, tags='arm isa')
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