d11c40dcac
This ensures `isort` is applied to all files in the repo. Change-Id: Ib7ced1c924ef1639542bf0d1a01c5737f6ba43e9
87 lines
3.2 KiB
Python
87 lines
3.2 KiB
Python
# Copyright 2021 Google, Inc.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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from m5.objects.ArmDecoder import ArmDecoder
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from m5.objects.ArmInterrupts import ArmInterrupts
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from m5.objects.ArmISA import ArmISA
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from m5.objects.ArmMMU import ArmMMU
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from m5.objects.BaseAtomicSimpleCPU import BaseAtomicSimpleCPU
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from m5.objects.BaseMinorCPU import BaseMinorCPU
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from m5.objects.BaseNonCachingSimpleCPU import BaseNonCachingSimpleCPU
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from m5.objects.BaseO3Checker import BaseO3Checker
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from m5.objects.BaseO3CPU import BaseO3CPU
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from m5.objects.BaseTimingSimpleCPU import BaseTimingSimpleCPU
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from m5.proxy import Self
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class ArmCPU:
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ArchDecoder = ArmDecoder
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ArchMMU = ArmMMU
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ArchInterrupts = ArmInterrupts
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ArchISA = ArmISA
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class ArmAtomicSimpleCPU(BaseAtomicSimpleCPU, ArmCPU):
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mmu = ArmMMU()
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class ArmNonCachingSimpleCPU(BaseNonCachingSimpleCPU, ArmCPU):
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mmu = ArmMMU()
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class ArmTimingSimpleCPU(BaseTimingSimpleCPU, ArmCPU):
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mmu = ArmMMU()
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class ArmO3Checker(BaseO3Checker, ArmCPU):
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mmu = ArmMMU()
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class ArmO3CPU(BaseO3CPU, ArmCPU):
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mmu = ArmMMU()
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# For x86, each CC reg is used to hold only a subset of the
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# flags, so we need 4-5 times the number of CC regs as
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# physical integer regs to be sure we don't run out. In
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# typical real machines, CC regs are not explicitly renamed
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# (it's a side effect of int reg renaming), so they should
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# never be the bottleneck here.
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numPhysCCRegs = Self.numPhysIntRegs * 5
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def addCheckerCpu(self):
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self.checker = ArmO3Checker(
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workload=self.workload,
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exitOnError=False,
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updateOnError=True,
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warnOnlyOnLoadError=True,
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)
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self.checker.mmu.itb.size = self.mmu.itb.size
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self.checker.mmu.dtb.size = self.mmu.dtb.size
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self.checker.cpu_id = self.cpu_id
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class ArmMinorCPU(BaseMinorCPU, ArmCPU):
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mmu = ArmMMU()
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