d4273cc9a6
This patch removes the notion of a peer block size and instead sets the cache line size on the system level. Previously the size was set per cache, and communicated through the interconnect. There were plenty checks to ensure that everyone had the same size specified, and these checks are now removed. Another benefit that is not yet harnessed is that the cache line size is now known at construction time, rather than after the port binding. Hence, the block size can be locally stored and does not have to be queried every time it is used. A follow-on patch updates the configuration scripts accordingly.
387 lines
11 KiB
C++
387 lines
11 KiB
C++
/*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Erik Hallnor
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* Steve Reinhardt
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*/
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// FIX ME: make trackBlkAddr use blocksize from actual cache, not hard coded
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#include <iomanip>
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#include <set>
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#include <string>
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#include <vector>
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#include "base/misc.hh"
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#include "base/statistics.hh"
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#include "cpu/testers/memtest/memtest.hh"
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#include "debug/MemTest.hh"
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#include "mem/mem_object.hh"
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#include "mem/packet.hh"
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#include "mem/port.hh"
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#include "mem/request.hh"
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#include "sim/sim_events.hh"
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#include "sim/stats.hh"
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#include "sim/system.hh"
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using namespace std;
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int TESTER_ALLOCATOR=0;
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bool
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MemTest::CpuPort::recvTimingResp(PacketPtr pkt)
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{
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memtest->completeRequest(pkt);
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return true;
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}
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void
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MemTest::CpuPort::recvRetry()
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{
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memtest->doRetry();
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}
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void
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MemTest::sendPkt(PacketPtr pkt) {
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if (atomic) {
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cachePort.sendAtomic(pkt);
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completeRequest(pkt);
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}
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else if (!cachePort.sendTimingReq(pkt)) {
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DPRINTF(MemTest, "accessRetry setting to true\n");
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//
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// dma requests should never be retried
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//
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if (issueDmas) {
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panic("Nacked DMA requests are not supported\n");
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}
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accessRetry = true;
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retryPkt = pkt;
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} else {
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if (issueDmas) {
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dmaOutstanding = true;
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}
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}
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}
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MemTest::MemTest(const Params *p)
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: MemObject(p),
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tickEvent(this),
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cachePort("test", this),
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funcPort("functional", this),
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funcProxy(funcPort, p->sys->cacheLineSize()),
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retryPkt(NULL),
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// mainMem(main_mem),
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// checkMem(check_mem),
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size(p->memory_size),
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percentReads(p->percent_reads),
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percentFunctional(p->percent_functional),
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percentUncacheable(p->percent_uncacheable),
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issueDmas(p->issue_dmas),
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masterId(p->sys->getMasterId(name())),
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blockSize(p->sys->cacheLineSize()),
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progressInterval(p->progress_interval),
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nextProgressMessage(p->progress_interval),
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percentSourceUnaligned(p->percent_source_unaligned),
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percentDestUnaligned(p->percent_dest_unaligned),
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maxLoads(p->max_loads),
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atomic(p->atomic),
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suppress_func_warnings(p->suppress_func_warnings)
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{
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id = TESTER_ALLOCATOR++;
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// Needs to be masked off once we know the block size.
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traceBlockAddr = p->trace_addr;
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baseAddr1 = 0x100000;
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baseAddr2 = 0x400000;
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uncacheAddr = 0x800000;
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blockAddrMask = blockSize - 1;
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traceBlockAddr = blockAddr(traceBlockAddr);
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// set up counters
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noResponseCycles = 0;
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numReads = 0;
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numWrites = 0;
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schedule(tickEvent, 0);
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accessRetry = false;
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dmaOutstanding = false;
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}
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BaseMasterPort &
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MemTest::getMasterPort(const std::string &if_name, PortID idx)
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{
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if (if_name == "functional")
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return funcPort;
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else if (if_name == "test")
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return cachePort;
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else
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return MemObject::getMasterPort(if_name, idx);
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}
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void
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MemTest::init()
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{
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// initial memory contents for both physical memory and functional
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// memory should be 0; no need to initialize them.
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}
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void
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MemTest::completeRequest(PacketPtr pkt)
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{
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Request *req = pkt->req;
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if (issueDmas) {
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dmaOutstanding = false;
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}
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DPRINTF(MemTest, "completing %s at address %x (blk %x) %s\n",
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pkt->isWrite() ? "write" : "read",
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req->getPaddr(), blockAddr(req->getPaddr()),
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pkt->isError() ? "error" : "success");
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MemTestSenderState *state =
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dynamic_cast<MemTestSenderState *>(pkt->senderState);
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uint8_t *data = state->data;
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uint8_t *pkt_data = pkt->getPtr<uint8_t>();
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//Remove the address from the list of outstanding
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std::set<unsigned>::iterator removeAddr =
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outstandingAddrs.find(req->getPaddr());
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assert(removeAddr != outstandingAddrs.end());
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outstandingAddrs.erase(removeAddr);
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if (pkt->isError()) {
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if (!suppress_func_warnings) {
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warn("Functional %s access failed at %#x\n",
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pkt->isWrite() ? "write" : "read", req->getPaddr());
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}
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} else {
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if (pkt->isRead()) {
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if (memcmp(pkt_data, data, pkt->getSize()) != 0) {
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panic("%s: read of %x (blk %x) @ cycle %d "
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"returns %x, expected %x\n", name(),
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req->getPaddr(), blockAddr(req->getPaddr()), curTick(),
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*pkt_data, *data);
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}
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numReads++;
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numReadsStat++;
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if (numReads == (uint64_t)nextProgressMessage) {
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ccprintf(cerr, "%s: completed %d read, %d write accesses @%d\n",
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name(), numReads, numWrites, curTick());
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nextProgressMessage += progressInterval;
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}
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if (maxLoads != 0 && numReads >= maxLoads)
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exitSimLoop("maximum number of loads reached");
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} else {
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assert(pkt->isWrite());
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funcProxy.writeBlob(req->getPaddr(), pkt_data, req->getSize());
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numWrites++;
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numWritesStat++;
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}
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}
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noResponseCycles = 0;
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delete state;
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delete [] data;
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delete pkt->req;
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delete pkt;
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}
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void
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MemTest::regStats()
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{
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using namespace Stats;
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numReadsStat
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.name(name() + ".num_reads")
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.desc("number of read accesses completed")
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;
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numWritesStat
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.name(name() + ".num_writes")
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.desc("number of write accesses completed")
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;
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numCopiesStat
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.name(name() + ".num_copies")
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.desc("number of copy accesses completed")
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;
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}
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void
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MemTest::tick()
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{
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if (!tickEvent.scheduled())
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schedule(tickEvent, clockEdge(Cycles(1)));
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if (++noResponseCycles >= 500000) {
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if (issueDmas) {
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cerr << "DMA tester ";
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}
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cerr << name() << ": deadlocked at cycle " << curTick() << endl;
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fatal("");
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}
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if (accessRetry || (issueDmas && dmaOutstanding)) {
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DPRINTF(MemTest, "MemTester waiting on accessRetry or DMA response\n");
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return;
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}
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//make new request
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unsigned cmd = random() % 100;
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unsigned offset = random() % size;
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unsigned base = random() % 2;
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uint64_t data = random();
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unsigned access_size = random() % 4;
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bool uncacheable = (random() % 100) < percentUncacheable;
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unsigned dma_access_size = random() % 4;
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//If we aren't doing copies, use id as offset, and do a false sharing
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//mem tester
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//We can eliminate the lower bits of the offset, and then use the id
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//to offset within the blks
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offset = blockAddr(offset);
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offset += id;
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access_size = 0;
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dma_access_size = 0;
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Request::Flags flags;
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Addr paddr;
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if (uncacheable) {
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flags.set(Request::UNCACHEABLE);
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paddr = uncacheAddr + offset;
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} else {
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paddr = ((base) ? baseAddr1 : baseAddr2) + offset;
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}
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// For now we only allow one outstanding request per address
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// per tester This means we assume CPU does write forwarding
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// to reads that alias something in the cpu store buffer.
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if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) {
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return;
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}
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bool do_functional = (random() % 100 < percentFunctional) && !uncacheable;
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Request *req = new Request();
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uint8_t *result = new uint8_t[8];
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if (issueDmas) {
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paddr &= ~((1 << dma_access_size) - 1);
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req->setPhys(paddr, 1 << dma_access_size, flags, masterId);
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req->setThreadContext(id,0);
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} else {
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paddr &= ~((1 << access_size) - 1);
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req->setPhys(paddr, 1 << access_size, flags, masterId);
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req->setThreadContext(id,0);
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}
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assert(req->getSize() == 1);
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if (cmd < percentReads) {
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// read
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outstandingAddrs.insert(paddr);
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// ***** NOTE FOR RON: I'm not sure how to access checkMem. - Kevin
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funcProxy.readBlob(req->getPaddr(), result, req->getSize());
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DPRINTF(MemTest,
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"id %d initiating %sread at addr %x (blk %x) expecting %x\n",
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id, do_functional ? "functional " : "", req->getPaddr(),
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blockAddr(req->getPaddr()), *result);
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PacketPtr pkt = new Packet(req, MemCmd::ReadReq);
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pkt->dataDynamicArray(new uint8_t[req->getSize()]);
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MemTestSenderState *state = new MemTestSenderState(result);
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pkt->senderState = state;
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if (do_functional) {
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assert(pkt->needsResponse());
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pkt->setSuppressFuncError();
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cachePort.sendFunctional(pkt);
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completeRequest(pkt);
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} else {
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sendPkt(pkt);
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}
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} else {
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// write
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outstandingAddrs.insert(paddr);
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DPRINTF(MemTest, "initiating %swrite at addr %x (blk %x) value %x\n",
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do_functional ? "functional " : "", req->getPaddr(),
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blockAddr(req->getPaddr()), data & 0xff);
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PacketPtr pkt = new Packet(req, MemCmd::WriteReq);
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uint8_t *pkt_data = new uint8_t[req->getSize()];
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pkt->dataDynamicArray(pkt_data);
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memcpy(pkt_data, &data, req->getSize());
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MemTestSenderState *state = new MemTestSenderState(result);
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pkt->senderState = state;
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if (do_functional) {
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pkt->setSuppressFuncError();
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cachePort.sendFunctional(pkt);
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completeRequest(pkt);
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} else {
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sendPkt(pkt);
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}
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}
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}
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void
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MemTest::doRetry()
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{
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if (cachePort.sendTimingReq(retryPkt)) {
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DPRINTF(MemTest, "accessRetry setting to false\n");
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accessRetry = false;
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retryPkt = NULL;
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}
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}
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void
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MemTest::printAddr(Addr a)
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{
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cachePort.printAddr(a);
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}
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MemTest *
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MemTestParams::create()
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{
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return new MemTest(this);
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}
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