Steve Reinhardt d172e1576a Split CachePort class into CpuSidePort and MemSidePort ...

and push those into derived Cache template class to
eliminate a few layers of virtual functions and
conditionals ("if (isCpuSide) { ... }" etc.).

--HG--
extra : convert_revision : cb1b88246c95b36aa0cf26d534127d3714ddb774

2006-12-13 22:04:36 -08:00

..

cache

Split CachePort class into CpuSidePort and MemSidePort

2006-12-13 22:04:36 -08:00

config

Backing in more changsets, getting closer to compile

2006-06-28 14:35:00 -04:00

bridge.cc

Update bus bridges now that snoop ranges are passed properly

2006-11-14 01:12:52 -05:00

bridge.hh

Use PacketPtr everywhere

2006-10-20 00:10:12 -07:00

bus.cc

Do a functional access to levels above on a read as a temporary solution for L2's in FS

2006-11-22 20:20:38 -05:00

bus.hh

Update atomic and functional paths for snoops as well

2006-11-14 01:38:42 -05:00

dram.cc

Use PacketPtr everywhere

2006-10-20 00:10:12 -07:00

dram.hh

Use PacketPtr everywhere

2006-10-20 00:10:12 -07:00

mem_object.cc

Updated Authors from bk prs info

2006-05-31 19:26:56 -04:00

mem_object.hh

Fix up doxygen.

2006-08-14 19:25:07 -04:00

packet_access.hh

refactor code for the packet, get rid of packet_impl.hh

2006-10-19 23:38:45 -07:00

packet.cc

Fix functional access errors related to delayed respnoses in cachePort

2006-11-12 06:35:39 -05:00

packet.hh

Fix bugs around uni-coherence invalidates being propogated properly.

2006-11-14 17:15:05 -05:00

page_table.cc

initialize end, clean up loop

2006-10-19 23:35:59 -07:00

page_table.hh

add code to serialize se structures. Lisa is working on the python side of things and will test

2006-10-17 19:38:36 -04:00

physical.cc

Physical memory overrides the tport version of recvFunctional, need to do the

2006-11-12 09:30:12 -05:00

physical.hh

Use PacketPtr everywhere

2006-10-20 00:10:12 -07:00

port_impl.hh

Put the ProcessInfo and StackTrace objects into the ISA namespaces.

2006-11-08 00:52:04 -05:00

port.cc

refactor code for the packet, get rid of packet_impl.hh

2006-10-19 23:38:45 -07:00

port.hh

Ports now have a pointer to the MemObject that owns it (can be NULL).

2006-10-31 13:59:30 -05:00

request.hh

Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing)

2006-10-08 10:53:24 -07:00

tport.cc

Don't insert reponses into the list more than once

2006-11-12 07:16:34 -05:00

tport.hh

Merge ktlim@zizzer:/bk/newmem

2006-10-31 14:37:19 -05:00

translating_port.cc

Updated Authors from bk prs info

2006-05-31 19:26:56 -04:00

translating_port.hh

Updated Authors from bk prs info

2006-05-31 19:26:56 -04:00

vport.cc

Fix up doxygen.

2006-08-14 19:25:07 -04:00

vport.hh

Fix up doxygen.

2006-08-14 19:25:07 -04:00