Gabe Black 3d7d426fa5 cpu: Generalize how register files are serialized. ...

Instead of explicitly serializing each type of register explicitly, and
using custom types, etc, store them as generic blocks of data. This lets
us get rid of the final use of TheISA::VecRegContainer and
TheISA::VecPredRegContainer.

Change-Id: I61dbd7825ffe35c41e1b7c8317590d06c21b4513
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50252
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>

2022-08-04 20:22:32 +00:00

..

arm-ccregs.py

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arm-contextidr-el2.py

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arm-gem5-gic-ext.py

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arm-gicv2-banked-regs.py

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arm-hdlcd-upgrade.py

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arm-miscreg-teehbr.py

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arm-sve.py

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arm-sysreg-mapping-ns.py

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armv8.py

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cpu-pid.py

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dvfs-perflevel.py

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etherswitch.py

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globals-to-root.py

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ide-dma-abort.py

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isa-is-simobject.py

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memory-per-range.py

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mempool-sections.py

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mempool-to-seworkload.py

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multiple-event-queues.py

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process-fdmap-rename.py

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register-files.py

cpu: Generalize how register files are serialized.

2022-08-04 20:22:32 +00:00

remove-arm-cpsr-mode-miscreg.py

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ruby-block-size-bytes.py

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smt-interrupts.py

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x86-add-tlb.py

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