Giacomo Travaglini 2e271459d0 mem-cache: Implementation of SMS prefetcher (#1454) ...

This PR adds the SMS prefetcher described in [this
](https://web.eecs.umich.edu/~twenisch/papers/isca06.pdf) paper.
This work was done in collaboration with @Setu-Gupta, and @xmlizhao

On branch sms
Changes to be committed:
modified: src/mem/cache/prefetch/Prefetcher.py
modified: src/mem/cache/prefetch/SConscript
new file: src/mem/cache/prefetch/sms.cc
new file: src/mem/cache/prefetch/sms.hh

Change-Id: I68d3bb6cf07385177d0f776fb958f652cfc41489

2024-10-18 19:15:57 +02:00

..

arch

arch-riscv: Implement Zcmp instructions (#1432)

2024-10-18 05:33:55 -07:00

base

tests: Fix compiler tests (#1678)

2024-10-17 11:19:46 -07:00

cpu

Implement BTB using the cache library (#1537)

2024-10-10 17:05:22 +01:00

dev

tests: Fix compiler tests (#1678)

2024-10-17 11:19:46 -07:00

doc

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doxygen

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gpu-compute

gpu-compute: Fix '64kB' to '64KiB' in gpu-compute (#1594)

2024-09-23 15:25:43 -07:00

kern

arch, sim-se: Fix off_t size mismatch bug

2024-08-20 16:18:24 +01:00

learning_gem5

configs, dev, learning-gem5, python, tests: more clarification

2024-08-23 18:02:42 -07:00

mem

mem-cache: Implementation of SMS prefetcher (#1454)

2024-10-18 19:15:57 +02:00

proto

scons: Use Kconfig to configure gem5.

2023-11-23 08:26:10 +08:00

python

arch-arm: Add arm demo board (#1478)

2024-10-18 05:36:31 -07:00

sim

sim: Make SignalSinkPort::set virtual (#1679)

2024-10-18 05:41:05 -07:00

sst

mem,arch-arm,mem-ruby,cpu: Remove use of deprecated base port owner

2023-02-03 06:11:45 +00:00

systemc

systemc: Disable 'overloaded-virtual' warn for clang (#1662)

2024-10-18 05:40:10 -07:00

test_objects

stdlib: Add SparseHist to PyStats

2024-05-23 14:54:59 -07:00

Doxyfile

misc: Update versioning for develop branch

2024-06-27 23:36:07 -07:00

Kconfig

scons,tests: Add 'USE_TEST_OBJECTS' kconfig

2024-04-04 13:04:21 -07:00

SConscript

python: Add importer to standalone gem5py_m5

2023-09-28 11:22:33 -07:00