5e767970d8
Before, for historical reasons, the PCI host device was the default responder on the IO bus, meaning that when there was any type of transaction which didn't have a device to go to, it would end up looking like a PCI config transaction. It's very unlikely that this is what it actually was, and what would happen would be arbitrary and probably not helpful. Also, there was no device in place to respond to accesses in x86's IO port address space. On a real system, these accesses just return junk and are otherwise legal. On systems where there would be physical bus wires they would probably return whatever the last data on the bus was. This would have been helpful when the platform was first being set up because it would make it obvious when the OS tried to access a device that wasn't implemented, but there were a few cases where it would purposefully fiddle with ports with nothing on them. These had one off backing devices in the config which would handle the accesses harmlessly, but if the OS changed and tried to access other ports, the configs would need to be updated. Now, the PCI host is just another device on the bus. It claims all of the PCI config space addresses, so any config access, even ones which don't go with a device, will go to it, and it can respond with all 1s like it's supposed to. In it's place, the default responder is now a bus. On that bus is a device which responds to the entire IO port address range with 0s. The default on *that* bus is a device which will mark any accesses as bad. With this setup, accesses which don't go to a device, including a device on the IO port address space, will go to the IO bus's default port. There, if the access was an IO access, it will go to the device which replies successfully with all 0s. If not, it's marked as an error. The device which backs the entire IO address space doesn't conflict with the actual IO devices, since the access will only go towards it if it's otherwise unclaimed, and the devices on the default bus don't participate in routing on the higher level IO bus. Change-Id: Ie02ad7165dfad3ee6f4a762e2f01f7f1b8225168 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35515 Reviewed-by: Matthew Poremba <matthew.poremba@amd.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
90 lines
3.7 KiB
Python
90 lines
3.7 KiB
Python
# Copyright (c) 2008 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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from m5.params import *
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from m5.proxy import *
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from m5.objects.Device import IsaFake, BadAddr
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from m5.objects.Platform import Platform
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from m5.objects.SouthBridge import SouthBridge
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from m5.objects.Terminal import Terminal
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from m5.objects.Uart import Uart8250
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from m5.objects.PciHost import GenericPciHost
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from m5.objects.XBar import IOXBar
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def x86IOAddress(port):
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IO_address_space_base = 0x8000000000000000
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return IO_address_space_base + port;
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class PcPciHost(GenericPciHost):
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conf_base = 0xC000000000000000
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conf_size = "16MB"
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pci_pio_base = 0x8000000000000000
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class Pc(Platform):
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type = 'Pc'
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cxx_header = "dev/x86/pc.hh"
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system = Param.System(Parent.any, "system")
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south_bridge = SouthBridge()
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pci_host = PcPciHost()
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# Serial port and terminal
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com_1 = Uart8250()
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com_1.pio_addr = x86IOAddress(0x3f8)
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com_1.device = Terminal()
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# Devices to catch access to non-existant serial ports.
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fake_com_2 = IsaFake(pio_addr=x86IOAddress(0x2f8), pio_size=8)
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fake_com_3 = IsaFake(pio_addr=x86IOAddress(0x3e8), pio_size=8)
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fake_com_4 = IsaFake(pio_addr=x86IOAddress(0x2e8), pio_size=8)
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# A device to catch accesses to the non-existant floppy controller.
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fake_floppy = IsaFake(pio_addr=x86IOAddress(0x3f2), pio_size=2)
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# A bus for accesses not claimed by a specific device.
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default_bus = IOXBar()
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# A device to handle accesses to unclaimed IO ports.
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empty_isa = IsaFake(pio_addr=x86IOAddress(0), pio_size='64kB',
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ret_data8=0, ret_data16=0, ret_data32=0, ret_data64=0,
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pio=default_bus.mem_side_ports)
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# A device to handle any other type of unclaimed access.
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bad_addr = BadAddr(pio=default_bus.default)
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def attachIO(self, bus, dma_ports = []):
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self.south_bridge.attachIO(bus, dma_ports)
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self.com_1.pio = bus.mem_side_ports
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self.fake_com_2.pio = bus.mem_side_ports
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self.fake_com_3.pio = bus.mem_side_ports
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self.fake_com_4.pio = bus.mem_side_ports
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self.fake_floppy.pio = bus.mem_side_ports
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self.pci_host.pio = bus.mem_side_ports
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self.default_bus.cpu_side_ports = bus.default
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