24da30e317
This basically means changing all #include statements and changing autogenerated code so that it generates the correct paths. Because slicc generates #includes, I had to hard code the include paths to mem/protocol.
393 lines
12 KiB
C++
393 lines
12 KiB
C++
/*
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* Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <stdio.h>
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#include "mem/ruby/network/orion/power_arbiter.hh"
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#include "mem/ruby/network/orion/power_array.hh"
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#include "mem/ruby/network/orion/power_ll.hh"
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#include "mem/ruby/network/orion/parm_technology.hh"
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#include "mem/ruby/network/orion/SIM_port.hh"
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#include "mem/ruby/network/orion/power_static.hh"
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#include "mem/ruby/network/orion/power_utils.hh"
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/******************************* Power model for flip flop *****************************/
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/* ------- flip flop model ---------- */
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/* this model is based on the gate-level design given by Randy H. Katz "Contemporary Logic Design"
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* Figure 6.24, node numbers (1-6) are assigned to all gate outputs, left to right, top to bottom
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*
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* We should have pure cap functions and leave the decision of whether or not to have coefficient
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* 1/2 in init function.
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*/
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static double SIM_fpfp_node_cap(unsigned fan_in, unsigned fan_out)
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{
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double Ctotal = 0;
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/* FIXME: all need actual sizes */
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/* part 1: drain cap of NOR gate */
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Ctotal += fan_in * SIM_power_draincap(WdecNORn, NCH, 1) + SIM_power_draincap(WdecNORp, PCH, fan_in);
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/* part 2: gate cap of NOR gates */
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Ctotal += fan_out * SIM_power_gatecap(WdecNORn + WdecNORp, 0);
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return Ctotal;
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}
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static double SIM_fpfp_clock_cap(void)
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{
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/* gate cap of clock load */
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return (2 * SIM_power_gatecap(WdecNORn + WdecNORp, 0));
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}
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int SIM_fpfp_clear_stat(power_ff *ff)
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{
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ff->n_switch = ff->n_keep_1 = ff->n_keep_0 = ff->n_clock = 0;
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return 0;
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}
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int SIM_fpfp_init(power_ff *ff, int model, double load)
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{
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double c1, c2, c3, c4, c5, c6;
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if ((ff->model = model) && model < FF_MAX_MODEL) {
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switch (model) {
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case NEG_DFF:
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SIM_fpfp_clear_stat(ff);
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/* node 5 and node 6 are identical to node 1 in capacitance */
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c1 = c5 = c6 = SIM_fpfp_node_cap(2, 1);
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c2 = SIM_fpfp_node_cap(2, 3);
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c3 = SIM_fpfp_node_cap(3, 2);
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c4 = SIM_fpfp_node_cap(2, 3);
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ff->e_switch = (c4 + c1 + c2 + c3 + c5 + c6 + load) / 2 * EnergyFactor;
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/* no 1/2 for e_keep and e_clock because clock signal switches twice in one cycle */
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ff->e_keep_1 = c3 * EnergyFactor;
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ff->e_keep_0 = c2 * EnergyFactor;
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ff->e_clock = SIM_fpfp_clock_cap() * EnergyFactor;
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/* static power */
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ff->i_leakage = (WdecNORp * NOR2_TAB[0] + WdecNORn * (NOR2_TAB[1] + NOR2_TAB[2] + NOR2_TAB[3])) / 4 * 6 / PARM_TECH_POINT * 100;
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break;
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default: break;/* some error handler */
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}
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return 0;
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}
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else
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return -1;
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}
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double SIM_fpfp_report(power_ff *ff)
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{
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return (ff->e_switch * ff->n_switch + ff->e_clock * ff->n_clock +
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ff->e_keep_0 * ff->n_keep_0 + ff->e_keep_1 * ff->n_keep_1);
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}
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/* ------- flip flop model ---------- */
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/* -------- arbiter power model ------------- */
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/* switch cap of request signal (round robin arbiter) */
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static double rr_arbiter_req_cap(double length)
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{
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double Ctotal = 0;
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/* part 1: gate cap of 2 NOR gates */
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/* FIXME: need actual size */
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Ctotal += 2 * SIM_power_gatecap(WdecNORn + WdecNORp, 0);
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/* part 2: inverter */
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/* FIXME: need actual size */
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Ctotal += SIM_power_draincap(Wdecinvn, NCH, 1) + SIM_power_draincap(Wdecinvp, PCH, 1) +
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SIM_power_gatecap(Wdecinvn + Wdecinvp, 0);
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/* part 3: wire cap */
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Ctotal += length * Cmetal;
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return Ctotal;
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}
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/* switch cap of priority signal (round robin arbiter) */
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static double rr_arbiter_pri_cap()
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{
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double Ctotal = 0;
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/* part 1: gate cap of NOR gate */
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/* FIXME: need actual size */
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Ctotal += SIM_power_gatecap(WdecNORn + WdecNORp, 0);
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return Ctotal;
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}
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/* switch cap of grant signal (round robin arbiter) */
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static double rr_arbiter_grant_cap()
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{
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double Ctotal = 0;
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/* part 1: drain cap of NOR gate */
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/* FIXME: need actual size */
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Ctotal += 2 * SIM_power_draincap(WdecNORn, NCH, 1) + SIM_power_draincap(WdecNORp, PCH, 2);
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return Ctotal;
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}
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/* switch cap of carry signal (round robin arbiter) */
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static double rr_arbiter_carry_cap()
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{
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double Ctotal = 0;
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/* part 1: drain cap of NOR gate (this block) */
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/* FIXME: need actual size */
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Ctotal += 2 * SIM_power_draincap(WdecNORn, NCH, 1) + SIM_power_draincap(WdecNORp, PCH, 2);
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/* part 2: gate cap of NOR gate (next block) */
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/* FIXME: need actual size */
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Ctotal += SIM_power_gatecap(WdecNORn + WdecNORp, 0);
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return Ctotal;
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}
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/* switch cap of internal carry node (round robin arbiter) */
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static double rr_arbiter_carry_in_cap()
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{
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double Ctotal = 0;
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/* part 1: gate cap of 2 NOR gates */
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/* FIXME: need actual size */
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Ctotal += 2 * SIM_power_gatecap(WdecNORn + WdecNORp, 0);
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/* part 2: drain cap of NOR gate */
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/* FIXME: need actual size */
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Ctotal += 2 * SIM_power_draincap(WdecNORn, NCH, 1) + SIM_power_draincap(WdecNORp, PCH, 2);
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return Ctotal;
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}
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/* the "huge" NOR gate in matrix arbiter model is an approximation */
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/* switch cap of request signal (matrix arbiter) */
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static double matrix_arbiter_req_cap(unsigned req_width, double length)
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{
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double Ctotal = 0;
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/* FIXME: all need actual sizes */
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/* part 1: gate cap of NOR gates */
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Ctotal += (req_width - 1) * SIM_power_gatecap(WdecNORn + WdecNORp, 0);
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/* part 2: inverter */
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Ctotal += SIM_power_draincap(Wdecinvn, NCH, 1) + SIM_power_draincap(Wdecinvp, PCH, 1) +
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SIM_power_gatecap(Wdecinvn + Wdecinvp, 0);
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/* part 3: gate cap of the "huge" NOR gate */
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Ctotal += SIM_power_gatecap(WdecNORn + WdecNORp, 0);
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/* part 4: wire cap */
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Ctotal += length * Cmetal;
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return Ctotal;
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}
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/* switch cap of priority signal (matrix arbiter) */
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static double matrix_arbiter_pri_cap(unsigned req_width)
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{
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double Ctotal = 0;
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/* part 1: gate cap of NOR gates (2 groups) */
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Ctotal += 2 * SIM_power_gatecap(WdecNORn + WdecNORp, 0);
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/* no inverter because priority signal is kept by a flip flop */
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return Ctotal;
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}
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/* switch cap of grant signal (matrix arbiter) */
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static double matrix_arbiter_grant_cap(unsigned req_width)
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{
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/* drain cap of the "huge" NOR gate */
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return (req_width * SIM_power_draincap(WdecNORn, NCH, 1) + SIM_power_draincap(WdecNORp, PCH, req_width));
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}
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/* switch cap of internal node (matrix arbiter) */
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static double matrix_arbiter_int_cap()
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{
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double Ctotal = 0;
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/* part 1: drain cap of NOR gate */
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Ctotal += 2 * SIM_power_draincap(WdecNORn, NCH, 1) + SIM_power_draincap(WdecNORp, PCH, 2);
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/* part 2: gate cap of the "huge" NOR gate */
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Ctotal += SIM_power_gatecap(WdecNORn + WdecNORp, 0);
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return Ctotal;
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}
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static int arbiter_clear_stat(power_arbiter *arb)
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{
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arb->n_chg_req = arb->n_chg_grant = arb->n_chg_mint = 0;
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arb->n_chg_carry = arb->n_chg_carry_in = 0;
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SIM_array_clear_stat(&arb->queue);
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SIM_fpfp_clear_stat(&arb->pri_ff);
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return 0;
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}
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int power_arbiter_init(power_arbiter *arb, int arbiter_model, int ff_model, unsigned req_width, double length, power_array_info *info)
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{
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if ((arb->model = arbiter_model) && arbiter_model < ARBITER_MAX_MODEL) {
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arb->req_width = req_width;
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arbiter_clear_stat(arb);
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/* redundant field */
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arb->mask = HAMM_MASK(req_width);
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switch (arbiter_model) {
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case RR_ARBITER:
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arb->e_chg_req = rr_arbiter_req_cap(length) / 2 * EnergyFactor;
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/* two grant signals switch together, so no 1/2 */
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arb->e_chg_grant = rr_arbiter_grant_cap() * EnergyFactor;
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arb->e_chg_carry = rr_arbiter_carry_cap() / 2 * EnergyFactor;
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arb->e_chg_carry_in = rr_arbiter_carry_in_cap() / 2 * EnergyFactor;
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arb->e_chg_mint = 0;
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if (SIM_fpfp_init(&arb->pri_ff, ff_model, rr_arbiter_pri_cap()))
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return -1;
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break;
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case MATRIX_ARBITER:
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arb->e_chg_req = matrix_arbiter_req_cap(req_width, length) / 2 * EnergyFactor;
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/* 2 grant signals switch together, so no 1/2 */
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arb->e_chg_grant = matrix_arbiter_grant_cap(req_width) * EnergyFactor;
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arb->e_chg_mint = matrix_arbiter_int_cap() / 2 * EnergyFactor;
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arb->e_chg_carry = arb->e_chg_carry_in = 0;
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if (SIM_fpfp_init(&arb->pri_ff, ff_model, matrix_arbiter_pri_cap(req_width)))
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return -1;
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break;
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case QUEUE_ARBITER:
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arb->e_chg_req = arb->e_chg_grant = arb->e_chg_mint = 0;
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arb->e_chg_carry = arb->e_chg_carry_in = 0;
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return power_array_init(info, &arb->queue);
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break;
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default: break;/* some error handler */
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}
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return 0;
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}
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else
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return -1;
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}
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int arbiter_record(power_arbiter *arb, unsigned long int new_req, unsigned long int old_req, unsigned new_grant, unsigned old_grant)
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{
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switch (arb->model) {
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case MATRIX_ARBITER:
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arb->n_chg_req += SIM_power_Hamming(new_req, old_req, arb->mask);
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arb->n_chg_grant += new_grant != old_grant;
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/* FIXME: approximation */
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arb->n_chg_mint += (arb->req_width - 1) * arb->req_width / 2;
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/* priority registers */
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/* FIXME: use average instead */
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arb->pri_ff.n_switch += (arb->req_width - 1) / 2;
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break;
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case RR_ARBITER:
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arb->n_chg_req += SIM_power_Hamming(new_req, old_req, arb->mask);
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arb->n_chg_grant += new_grant != old_grant;
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/* FIXME: use average instead */
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arb->n_chg_carry += arb->req_width / 2;
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arb->n_chg_carry_in += arb->req_width / 2 - 1;
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/* priority registers */
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arb->pri_ff.n_switch += 2;
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break;
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case QUEUE_ARBITER:
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break;
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default: break;/* some error handler */
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}
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return 0;
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}
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double arbiter_report(power_arbiter *arb)
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{
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switch (arb->model) {
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case MATRIX_ARBITER:
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return (arb->n_chg_req * arb->e_chg_req + arb->n_chg_grant * arb->e_chg_grant +
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arb->n_chg_mint * arb->e_chg_mint +
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arb->pri_ff.n_switch * arb->pri_ff.e_switch +
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arb->pri_ff.n_keep_1 * arb->pri_ff.e_keep_1 +
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arb->pri_ff.n_keep_0 * arb->pri_ff.e_keep_0 +
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arb->pri_ff.n_clock * arb->pri_ff.e_clock);
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case RR_ARBITER:
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return (arb->n_chg_req * arb->e_chg_req + arb->n_chg_grant * arb->e_chg_grant +
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arb->n_chg_carry * arb->e_chg_carry + arb->n_chg_carry_in * arb->e_chg_carry_in +
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arb->pri_ff.n_switch * arb->pri_ff.e_switch +
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arb->pri_ff.n_keep_1 * arb->pri_ff.e_keep_1 +
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arb->pri_ff.n_keep_0 * arb->pri_ff.e_keep_0 +
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arb->pri_ff.n_clock * arb->pri_ff.e_clock);
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default: return -1;
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}
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}
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/* ---------- arbiter power model ----------- */
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