934523c3a0
--HG-- rename : src/dev/alpha/AlphaConsole.py => src/dev/alpha/AlphaBackdoor.py rename : src/dev/alpha/console.cc => src/dev/alpha/backdoor.cc rename : src/dev/alpha/console.hh => src/dev/alpha/backdoor.hh
124 lines
5.0 KiB
Python
124 lines
5.0 KiB
Python
# Copyright (c) 2005-2007 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Nathan Binkert
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from m5.params import *
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from m5.proxy import *
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from BadDevice import BadDevice
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from AlphaBackdoor import AlphaBackdoor
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from Device import BasicPioDevice, IsaFake, BadAddr
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from Pci import PciConfigAll
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from Platform import Platform
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from Uart import Uart8250
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class TsunamiCChip(BasicPioDevice):
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type = 'TsunamiCChip'
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tsunami = Param.Tsunami(Parent.any, "Tsunami")
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class TsunamiIO(BasicPioDevice):
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type = 'TsunamiIO'
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time = Param.Time('01/01/2009',
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"System time to use ('Now' for actual time)")
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year_is_bcd = Param.Bool(False,
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"The RTC should interpret the year as a BCD value")
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tsunami = Param.Tsunami(Parent.any, "Tsunami")
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frequency = Param.Frequency('1024Hz', "frequency of interrupts")
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class TsunamiPChip(BasicPioDevice):
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type = 'TsunamiPChip'
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tsunami = Param.Tsunami(Parent.any, "Tsunami")
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class Tsunami(Platform):
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type = 'Tsunami'
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system = Param.System(Parent.any, "system")
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cchip = TsunamiCChip(pio_addr=0x801a0000000)
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pchip = TsunamiPChip(pio_addr=0x80180000000)
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pciconfig = PciConfigAll()
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fake_sm_chip = IsaFake(pio_addr=0x801fc000370)
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fake_uart1 = IsaFake(pio_addr=0x801fc0002f8)
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fake_uart2 = IsaFake(pio_addr=0x801fc0003e8)
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fake_uart3 = IsaFake(pio_addr=0x801fc0002e8)
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fake_uart4 = IsaFake(pio_addr=0x801fc0003f0)
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fake_ppc = IsaFake(pio_addr=0x801fc0003bb)
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fake_OROM = IsaFake(pio_addr=0x800000a0000, pio_size=0x60000)
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fake_pnp_addr = IsaFake(pio_addr=0x801fc000279)
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fake_pnp_write = IsaFake(pio_addr=0x801fc000a79)
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fake_pnp_read0 = IsaFake(pio_addr=0x801fc000203)
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fake_pnp_read1 = IsaFake(pio_addr=0x801fc000243)
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fake_pnp_read2 = IsaFake(pio_addr=0x801fc000283)
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fake_pnp_read3 = IsaFake(pio_addr=0x801fc0002c3)
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fake_pnp_read4 = IsaFake(pio_addr=0x801fc000303)
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fake_pnp_read5 = IsaFake(pio_addr=0x801fc000343)
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fake_pnp_read6 = IsaFake(pio_addr=0x801fc000383)
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fake_pnp_read7 = IsaFake(pio_addr=0x801fc0003c3)
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fake_ata0 = IsaFake(pio_addr=0x801fc0001f0)
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fake_ata1 = IsaFake(pio_addr=0x801fc000170)
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fb = BadDevice(pio_addr=0x801fc0003d0, devicename='FrameBuffer')
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io = TsunamiIO(pio_addr=0x801fc000000)
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uart = Uart8250(pio_addr=0x801fc0003f8)
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backdoor = AlphaBackdoor(pio_addr=0x80200000000, disk=Parent.simple_disk)
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# Attach I/O devices to specified bus object. Can't do this
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# earlier, since the bus object itself is typically defined at the
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# System level.
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def attachIO(self, bus):
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self.cchip.pio = bus.port
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self.pchip.pio = bus.port
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self.pciconfig.pio = bus.default
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bus.responder_set = True
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bus.responder = self.pciconfig
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self.fake_sm_chip.pio = bus.port
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self.fake_uart1.pio = bus.port
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self.fake_uart2.pio = bus.port
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self.fake_uart3.pio = bus.port
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self.fake_uart4.pio = bus.port
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self.fake_ppc.pio = bus.port
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self.fake_OROM.pio = bus.port
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self.fake_pnp_addr.pio = bus.port
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self.fake_pnp_write.pio = bus.port
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self.fake_pnp_read0.pio = bus.port
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self.fake_pnp_read1.pio = bus.port
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self.fake_pnp_read2.pio = bus.port
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self.fake_pnp_read3.pio = bus.port
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self.fake_pnp_read4.pio = bus.port
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self.fake_pnp_read5.pio = bus.port
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self.fake_pnp_read6.pio = bus.port
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self.fake_pnp_read7.pio = bus.port
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self.fake_ata0.pio = bus.port
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self.fake_ata1.pio = bus.port
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self.fb.pio = bus.port
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self.io.pio = bus.port
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self.uart.pio = bus.port
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self.backdoor.pio = bus.port
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