cc3d75ad72
This namespace has gone through the deprecation period and can now be removed. Change-Id: I87b763fccfcdf720909dfbda9c3fc8f6dea36a61 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67362 Tested-by: kokoro <noreply+kokoro@google.com>
100 lines
4.1 KiB
C++
100 lines
4.1 KiB
C++
/*
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* Copyright (c) 2007-2008 The Florida State University
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* Copyright (c) 2009 The University of Edinburgh
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* Copyright (c) 2021 IBM Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __POWER_PROCESS_HH__
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#define __POWER_PROCESS_HH__
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#include "sim/process.hh"
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namespace gem5
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{
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namespace loader
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{
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class ObjectFile;
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} // namespace loader
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class PowerProcess : public Process
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{
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protected:
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void initState() override;
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public:
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PowerProcess(const ProcessParams ¶ms, loader::ObjectFile *objFile);
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template <typename IntType>
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void argsInit(int pageSize);
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};
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} // namespace gem5
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enum PowerHWCAPFeature
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{
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HWCAP_FEATURE_32 = 1ULL << 31, // Always set for powerpc64
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HWCAP_FEATURE_64 = 1ULL << 30, // Always set for powerpc64
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HWCAP_FEATURE_HAS_ALTIVEC = 1ULL << 28,
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HWCAP_FEATURE_HAS_FPU = 1ULL << 27,
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HWCAP_FEATURE_HAS_MMU = 1ULL << 26,
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HWCAP_FEATURE_UNIFIED_CACHE = 1ULL << 24,
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HWCAP_FEATURE_NO_TB = 1ULL << 20, // 601/403gx have no timebase
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HWCAP_FEATURE_POWER4 = 1ULL << 19, // POWER4 ISA 2.00
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HWCAP_FEATURE_POWER5 = 1ULL << 18, // POWER5 ISA 2.02
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HWCAP_FEATURE_POWER5_PLUS = 1ULL << 17, // POWER5+ ISA 2.03
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HWCAP_FEATURE_CELL_BE = 1ULL << 16, // CELL Broadband Engine
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HWCAP_FEATURE_BOOKE = 1ULL << 15, // ISA Category Embedded
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HWCAP_FEATURE_SMT = 1ULL << 14, // Simultaneous Multi-Threading
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HWCAP_FEATURE_ICACHE_SNOOP = 1ULL << 13,
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HWCAP_FEATURE_ARCH_2_05 = 1ULL << 12, // ISA 2.05
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HWCAP_FEATURE_PA6T = 1ULL << 11, // PA Semi 6T Core
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HWCAP_FEATURE_HAS_DFP = 1ULL << 10, // Decimal FP Unit
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HWCAP_FEATURE_POWER6_EXT = 1ULL << 9, // P6 + mffgpr/mftgpr
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HWCAP_FEATURE_ARCH_2_06 = 1ULL << 8, // ISA 2.06
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HWCAP_FEATURE_HAS_VSX = 1ULL << 7, // P7 Vector Extension
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HWCAP_FEATURE_PSERIES_PERFMON_COMPAT = 1ULL << 6,
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HWCAP_FEATURE_TRUE_LE = 1ULL << 1,
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HWCAP_FEATURE_PPC_LE = 1ULL << 0
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};
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enum PowerHWCAP2Feature
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{
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HWCAP2_FEATURE_ARCH_2_07 = 1ULL << 31, // ISA 2.07
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HWCAP2_FEATURE_HAS_HTM = 1ULL << 30, // Hardware Transactional Memory
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HWCAP2_FEATURE_HAS_DSCR = 1ULL << 29, // Data Stream Control Register
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HWCAP2_FEATURE_HAS_EBB = 1ULL << 28, // Event Base Branching
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HWCAP2_FEATURE_HAS_ISEL = 1ULL << 27, // Integer Select
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HWCAP2_FEATURE_HAS_TAR = 1ULL << 26, // Target Address Register
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HWCAP2_FEATURE_HAS_VCRYPTO = 1ULL << 25, // Vector AES category
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HWCAP2_FEATURE_HTM_NOSC = 1ULL << 24,
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HWCAP2_FEATURE_ARCH_3_00 = 1ULL << 23, // ISA 3.0
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HWCAP2_FEATURE_HAS_IEEE128 = 1ULL << 22, // VSX IEEE Binary Float 128-bit
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};
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#endif // __POWER_PROCESS_HH__
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