cc03cf8270
This makes the device IntSlavePort calls back into based on a template parameter so that IntDevice doesn't have to be in the inheritance hierarchy to use it. It also makes IntSlavePort inherit from SimpleTimingPort directly, skipping over MessageSlavePort. Change-Id: Ic3213edc9c3ed5e506ee1e9f5e082cd47d7c7998 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20820 Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
138 lines
4.2 KiB
C++
138 lines
4.2 KiB
C++
/*
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* Copyright (c) 2012 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2008 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#ifndef __DEV_X86_INTDEV_HH__
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#define __DEV_X86_INTDEV_HH__
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#include <cassert>
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#include <list>
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#include <string>
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#include "arch/x86/intmessage.hh"
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#include "arch/x86/x86_traits.hh"
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#include "mem/mport.hh"
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#include "sim/sim_object.hh"
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namespace X86ISA {
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template <class Device>
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class IntSlavePort : public SimpleTimingPort
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{
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Device * device;
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public:
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IntSlavePort(const std::string& _name, SimObject* _parent,
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Device* dev) :
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SimpleTimingPort(_name, _parent), device(dev)
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{
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}
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AddrRangeList
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getAddrRanges() const
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{
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return device->getIntAddrRange();
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}
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Tick
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recvAtomic(PacketPtr pkt)
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{
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panic_if(pkt->cmd != MemCmd::MessageReq,
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"%s received unexpected command %s from %s.\n",
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name(), pkt->cmd.toString(), getPeer());
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pkt->headerDelay = pkt->payloadDelay = 0;
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return device->recvMessage(pkt);
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}
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};
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typedef std::list<int> ApicList;
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class IntDevice
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{
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protected:
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class IntMasterPort : public MessageMasterPort
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{
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IntDevice* device;
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Tick latency;
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public:
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IntMasterPort(const std::string& _name, SimObject* _parent,
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IntDevice* dev, Tick _latency) :
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MessageMasterPort(_name, _parent), device(dev), latency(_latency)
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{
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}
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Tick recvResponse(PacketPtr pkt)
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{
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return device->recvResponse(pkt);
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}
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// This is x86 focused, so if this class becomes generic, this would
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// need to be moved into a subclass.
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void sendMessage(ApicList apics,
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TriggerIntMessage message, bool timing);
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};
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IntMasterPort intMasterPort;
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public:
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IntDevice(SimObject * parent, Tick latency = 0) :
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intMasterPort(parent->name() + ".int_master", parent, this, latency)
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{
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}
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virtual ~IntDevice()
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{}
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virtual void init();
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virtual Tick
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recvResponse(PacketPtr pkt)
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{
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panic("recvResponse not implemented.\n");
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return 0;
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}
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};
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} // namespace X86ISA
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#endif //__DEV_X86_INTDEV_HH__
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