cba3a125e1
Some versions of the kernel incorrectly swap the red and blue color select registers. This changeset adds a workaround for that by swapping them when instantiating a PixelConverter.
626 lines
28 KiB
Python
626 lines
28 KiB
Python
# Copyright (c) 2009-2015 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Copyright (c) 2006-2007 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Ali Saidi
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# Gabe Black
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# William Wang
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from m5.params import *
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from m5.proxy import *
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from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice
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from Pci import PciConfigAll
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from Ethernet import NSGigE, IGbE_igb, IGbE_e1000
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from Ide import *
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from Platform import Platform
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from Terminal import Terminal
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from Uart import Uart
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from SimpleMemory import SimpleMemory
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from Gic import *
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from EnergyCtrl import EnergyCtrl
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class AmbaPioDevice(BasicPioDevice):
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type = 'AmbaPioDevice'
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abstract = True
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cxx_header = "dev/arm/amba_device.hh"
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amba_id = Param.UInt32("ID of AMBA device for kernel detection")
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class AmbaIntDevice(AmbaPioDevice):
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type = 'AmbaIntDevice'
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abstract = True
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cxx_header = "dev/arm/amba_device.hh"
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gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
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int_num = Param.UInt32("Interrupt number that connects to GIC")
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int_delay = Param.Latency("100ns",
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"Time between action and interrupt generation by device")
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class AmbaDmaDevice(DmaDevice):
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type = 'AmbaDmaDevice'
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abstract = True
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cxx_header = "dev/arm/amba_device.hh"
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pio_addr = Param.Addr("Address for AMBA slave interface")
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pio_latency = Param.Latency("10ns", "Time between action and write/read result by AMBA DMA Device")
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gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
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int_num = Param.UInt32("Interrupt number that connects to GIC")
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amba_id = Param.UInt32("ID of AMBA device for kernel detection")
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class A9SCU(BasicPioDevice):
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type = 'A9SCU'
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cxx_header = "dev/arm/a9scu.hh"
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class RealViewCtrl(BasicPioDevice):
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type = 'RealViewCtrl'
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cxx_header = "dev/arm/rv_ctrl.hh"
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proc_id0 = Param.UInt32(0x0C000000, "Processor ID, SYS_PROCID")
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proc_id1 = Param.UInt32(0x0C000222, "Processor ID, SYS_PROCID1")
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idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID")
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class VGic(PioDevice):
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type = 'VGic'
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cxx_header = "dev/arm/vgic.hh"
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gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
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platform = Param.Platform(Parent.any, "Platform this device is part of.")
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vcpu_addr = Param.Addr(0, "Address for vcpu interfaces")
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hv_addr = Param.Addr(0, "Address for hv control")
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pio_delay = Param.Latency('10ns', "Delay for PIO r/w")
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# The number of list registers is not currently configurable at runtime.
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ppint = Param.UInt32("HV maintenance interrupt number")
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class AmbaFake(AmbaPioDevice):
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type = 'AmbaFake'
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cxx_header = "dev/arm/amba_fake.hh"
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ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)")
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amba_id = 0;
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class Pl011(Uart):
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type = 'Pl011'
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cxx_header = "dev/arm/pl011.hh"
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gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
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int_num = Param.UInt32("Interrupt number that connects to GIC")
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end_on_eot = Param.Bool(False, "End the simulation when a EOT is received on the UART")
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int_delay = Param.Latency("100ns", "Time between action and interrupt generation by UART")
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class Sp804(AmbaPioDevice):
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type = 'Sp804'
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cxx_header = "dev/arm/timer_sp804.hh"
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gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
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int_num0 = Param.UInt32("Interrupt number that connects to GIC")
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clock0 = Param.Clock('1MHz', "Clock speed of the input")
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int_num1 = Param.UInt32("Interrupt number that connects to GIC")
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clock1 = Param.Clock('1MHz', "Clock speed of the input")
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amba_id = 0x00141804
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class CpuLocalTimer(BasicPioDevice):
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type = 'CpuLocalTimer'
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cxx_header = "dev/arm/timer_cpulocal.hh"
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gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
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int_num_timer = Param.UInt32("Interrrupt number used per-cpu to GIC")
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int_num_watchdog = Param.UInt32("Interrupt number for per-cpu watchdog to GIC")
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class GenericTimer(SimObject):
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type = 'GenericTimer'
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cxx_header = "dev/arm/generic_timer.hh"
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system = Param.System(Parent.any, "system")
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gic = Param.BaseGic(Parent.any, "GIC to use for interrupting")
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int_num = Param.UInt32("Interrupt number used per-cpu to GIC")
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# @todo: for now only one timer per CPU is supported, which is the
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# normal behaviour when Security and Virt. extensions are disabled.
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class PL031(AmbaIntDevice):
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type = 'PL031'
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cxx_header = "dev/arm/rtc_pl031.hh"
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time = Param.Time('01/01/2009', "System time to use ('Now' for actual time)")
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amba_id = 0x00341031
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class Pl050(AmbaIntDevice):
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type = 'Pl050'
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cxx_header = "dev/arm/kmi.hh"
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vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display")
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is_mouse = Param.Bool(False, "Is this interface a mouse, if not a keyboard")
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int_delay = '1us'
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amba_id = 0x00141050
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class Pl111(AmbaDmaDevice):
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type = 'Pl111'
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cxx_header = "dev/arm/pl111.hh"
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pixel_clock = Param.Clock('24MHz', "Pixel clock")
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vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display")
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amba_id = 0x00141111
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enable_capture = Param.Bool(True, "capture frame to system.framebuffer.bmp")
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class HDLcd(AmbaDmaDevice):
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type = 'HDLcd'
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cxx_header = "dev/arm/hdlcd.hh"
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# For reference, 1024x768MR-16@60 ~= 56 MHz
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# 1920x1080MR-16@60 ~= 137 MHz
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# 3840x2160MR-16@60 ~= 533 MHz
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# Match against the resolution selected in the Linux DTS/DTB file.
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pixel_clock = Param.Clock('137MHz', "Clock frequency of the pixel clock "
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"(i.e. PXLREFCLK / OSCCLK 5")
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vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer "
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"display")
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amba_id = 0x00141000
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workaround_swap_rb = Param.Bool(True, "Workaround incorrect color "
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"selector order in some kernels")
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enable_capture = Param.Bool(True, "capture frame to system.framebuffer.bmp")
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class RealView(Platform):
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type = 'RealView'
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cxx_header = "dev/arm/realview.hh"
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system = Param.System(Parent.any, "system")
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pci_io_base = Param.Addr(0, "Base address of PCI IO Space")
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pci_cfg_base = Param.Addr(0, "Base address of PCI Configuraiton Space")
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pci_cfg_gen_offsets = Param.Bool(False, "Should the offsets used for PCI cfg access"
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" be compatible with the pci-generic-host or the legacy host bridge?")
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_mem_regions = [(Addr(0), Addr('256MB'))]
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def attachPciDevices(self):
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pass
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def enableMSIX(self):
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pass
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def onChipIOClkDomain(self, clkdomain):
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pass
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def offChipIOClkDomain(self, clkdomain):
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pass
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def setupBootLoader(self, mem_bus, cur_sys, loc):
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self.nvmem = SimpleMemory(range = AddrRange('2GB', size = '64MB'),
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conf_table_reported = False)
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self.nvmem.port = mem_bus.master
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cur_sys.boot_loader = loc('boot.arm')
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cur_sys.atags_addr = 0x100
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cur_sys.load_addr_mask = 0xfffffff
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cur_sys.load_offset = 0
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# Reference for memory map and interrupt number
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# RealView Platform Baseboard Explore for Cortex-A9 User Guide(ARM DUI 0440A)
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# Chapter 4: Programmer's Reference
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class RealViewPBX(RealView):
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uart = Pl011(pio_addr=0x10009000, int_num=44)
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realview_io = RealViewCtrl(pio_addr=0x10000000)
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gic = Pl390()
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timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000)
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timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000)
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local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x1f000600)
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clcd = Pl111(pio_addr=0x10020000, int_num=55)
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kmi0 = Pl050(pio_addr=0x10006000, int_num=52)
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kmi1 = Pl050(pio_addr=0x10007000, int_num=53, is_mouse=True)
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a9scu = A9SCU(pio_addr=0x1f000000)
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cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=7, pci_bus=2,
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io_shift = 1, ctrl_offset = 2, Command = 0x1,
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BAR0 = 0x18000000, BAR0Size = '16B',
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BAR1 = 0x18000100, BAR1Size = '1B',
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BAR0LegacyIO = True, BAR1LegacyIO = True)
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l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff)
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flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000,
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fake_mem=True)
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dmac_fake = AmbaFake(pio_addr=0x10030000)
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uart1_fake = AmbaFake(pio_addr=0x1000a000)
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uart2_fake = AmbaFake(pio_addr=0x1000b000)
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uart3_fake = AmbaFake(pio_addr=0x1000c000)
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smc_fake = AmbaFake(pio_addr=0x100e1000)
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sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True)
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watchdog_fake = AmbaFake(pio_addr=0x10010000)
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gpio0_fake = AmbaFake(pio_addr=0x10013000)
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gpio1_fake = AmbaFake(pio_addr=0x10014000)
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gpio2_fake = AmbaFake(pio_addr=0x10015000)
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ssp_fake = AmbaFake(pio_addr=0x1000d000)
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sci_fake = AmbaFake(pio_addr=0x1000e000)
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aaci_fake = AmbaFake(pio_addr=0x10004000)
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mmc_fake = AmbaFake(pio_addr=0x10005000)
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rtc = PL031(pio_addr=0x10017000, int_num=42)
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energy_ctrl = EnergyCtrl(pio_addr=0x1000f000)
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# Attach I/O devices that are on chip and also set the appropriate
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# ranges for the bridge
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def attachOnChipIO(self, bus, bridge):
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self.gic.pio = bus.master
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self.l2x0_fake.pio = bus.master
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self.a9scu.pio = bus.master
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self.local_cpu_timer.pio = bus.master
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# Bridge ranges based on excluding what is part of on-chip I/O
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# (gic, l2x0, a9scu, local_cpu_timer)
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bridge.ranges = [AddrRange(self.realview_io.pio_addr,
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self.a9scu.pio_addr - 1),
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AddrRange(self.flash_fake.pio_addr,
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self.flash_fake.pio_addr + \
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self.flash_fake.pio_size - 1)]
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# Set the clock domain for IO objects that are considered
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# to be "close" to the cores.
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def onChipIOClkDomain(self, clkdomain):
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self.gic.clk_domain = clkdomain
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self.l2x0_fake.clk_domain = clkdomain
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self.a9scu.clkdomain = clkdomain
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self.local_cpu_timer.clk_domain = clkdomain
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# Attach I/O devices to specified bus object. Can't do this
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# earlier, since the bus object itself is typically defined at the
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# System level.
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def attachIO(self, bus):
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self.uart.pio = bus.master
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self.realview_io.pio = bus.master
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self.timer0.pio = bus.master
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self.timer1.pio = bus.master
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self.clcd.pio = bus.master
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self.clcd.dma = bus.slave
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self.kmi0.pio = bus.master
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self.kmi1.pio = bus.master
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self.cf_ctrl.pio = bus.master
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self.cf_ctrl.config = bus.master
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self.cf_ctrl.dma = bus.slave
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self.dmac_fake.pio = bus.master
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self.uart1_fake.pio = bus.master
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self.uart2_fake.pio = bus.master
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self.uart3_fake.pio = bus.master
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self.smc_fake.pio = bus.master
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self.sp810_fake.pio = bus.master
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self.watchdog_fake.pio = bus.master
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self.gpio0_fake.pio = bus.master
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self.gpio1_fake.pio = bus.master
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self.gpio2_fake.pio = bus.master
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self.ssp_fake.pio = bus.master
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self.sci_fake.pio = bus.master
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self.aaci_fake.pio = bus.master
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self.mmc_fake.pio = bus.master
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self.rtc.pio = bus.master
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self.flash_fake.pio = bus.master
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self.energy_ctrl.pio = bus.master
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# Set the clock domain for IO objects that are considered
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# to be "far" away from the cores.
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def offChipIOClkDomain(self, clkdomain):
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self.uart.clk_domain = clkdomain
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self.realview_io.clk_domain = clkdomain
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self.timer0.clk_domain = clkdomain
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self.timer1.clk_domain = clkdomain
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self.clcd.clk_domain = clkdomain
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self.kmi0.clk_domain = clkdomain
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self.kmi1.clk_domain = clkdomain
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self.cf_ctrl.clk_domain = clkdomain
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self.dmac_fake.clk_domain = clkdomain
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self.uart1_fake.clk_domain = clkdomain
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self.uart2_fake.clk_domain = clkdomain
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self.uart3_fake.clk_domain = clkdomain
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self.smc_fake.clk_domain = clkdomain
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self.sp810_fake.clk_domain = clkdomain
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self.watchdog_fake.clk_domain = clkdomain
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self.gpio0_fake.clk_domain = clkdomain
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self.gpio1_fake.clk_domain = clkdomain
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self.gpio2_fake.clk_domain = clkdomain
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self.ssp_fake.clk_domain = clkdomain
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self.sci_fake.clk_domain = clkdomain
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self.aaci_fake.clk_domain = clkdomain
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self.mmc_fake.clk_domain = clkdomain
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self.rtc.clk_domain = clkdomain
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self.flash_fake.clk_domain = clkdomain
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self.energy_ctrl.clk_domain = clkdomain
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# Reference for memory map and interrupt number
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# RealView Emulation Baseboard User Guide (ARM DUI 0143B)
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# Chapter 4: Programmer's Reference
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class RealViewEB(RealView):
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uart = Pl011(pio_addr=0x10009000, int_num=44)
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realview_io = RealViewCtrl(pio_addr=0x10000000, idreg=0x01400500)
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gic = Pl390(dist_addr=0x10041000, cpu_addr=0x10040000)
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timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000)
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timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000)
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clcd = Pl111(pio_addr=0x10020000, int_num=23)
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kmi0 = Pl050(pio_addr=0x10006000, int_num=20)
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kmi1 = Pl050(pio_addr=0x10007000, int_num=21, is_mouse=True)
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l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1")
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flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000-1,
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fake_mem=True)
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dmac_fake = AmbaFake(pio_addr=0x10030000)
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uart1_fake = AmbaFake(pio_addr=0x1000a000)
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uart2_fake = AmbaFake(pio_addr=0x1000b000)
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uart3_fake = AmbaFake(pio_addr=0x1000c000)
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smcreg_fake = IsaFake(pio_addr=0x10080000, pio_size=0x10000-1)
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smc_fake = AmbaFake(pio_addr=0x100e1000)
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sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True)
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watchdog_fake = AmbaFake(pio_addr=0x10010000)
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gpio0_fake = AmbaFake(pio_addr=0x10013000)
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gpio1_fake = AmbaFake(pio_addr=0x10014000)
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gpio2_fake = AmbaFake(pio_addr=0x10015000)
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ssp_fake = AmbaFake(pio_addr=0x1000d000)
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sci_fake = AmbaFake(pio_addr=0x1000e000)
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aaci_fake = AmbaFake(pio_addr=0x10004000)
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mmc_fake = AmbaFake(pio_addr=0x10005000)
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rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031)
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energy_ctrl = EnergyCtrl(pio_addr=0x1000f000)
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# Attach I/O devices that are on chip and also set the appropriate
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# ranges for the bridge
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def attachOnChipIO(self, bus, bridge):
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self.gic.pio = bus.master
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self.l2x0_fake.pio = bus.master
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# Bridge ranges based on excluding what is part of on-chip I/O
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# (gic, l2x0)
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bridge.ranges = [AddrRange(self.realview_io.pio_addr,
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self.gic.cpu_addr - 1),
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AddrRange(self.flash_fake.pio_addr, Addr.max)]
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# Set the clock domain for IO objects that are considered
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|
# to be "close" to the cores.
|
|
def onChipIOClkDomain(self, clkdomain):
|
|
self.gic.clk_domain = clkdomain
|
|
self.l2x0_fake.clk_domain = clkdomain
|
|
|
|
# Attach I/O devices to specified bus object. Can't do this
|
|
# earlier, since the bus object itself is typically defined at the
|
|
# System level.
|
|
def attachIO(self, bus):
|
|
self.uart.pio = bus.master
|
|
self.realview_io.pio = bus.master
|
|
self.timer0.pio = bus.master
|
|
self.timer1.pio = bus.master
|
|
self.clcd.pio = bus.master
|
|
self.clcd.dma = bus.slave
|
|
self.kmi0.pio = bus.master
|
|
self.kmi1.pio = bus.master
|
|
self.dmac_fake.pio = bus.master
|
|
self.uart1_fake.pio = bus.master
|
|
self.uart2_fake.pio = bus.master
|
|
self.uart3_fake.pio = bus.master
|
|
self.smc_fake.pio = bus.master
|
|
self.sp810_fake.pio = bus.master
|
|
self.watchdog_fake.pio = bus.master
|
|
self.gpio0_fake.pio = bus.master
|
|
self.gpio1_fake.pio = bus.master
|
|
self.gpio2_fake.pio = bus.master
|
|
self.ssp_fake.pio = bus.master
|
|
self.sci_fake.pio = bus.master
|
|
self.aaci_fake.pio = bus.master
|
|
self.mmc_fake.pio = bus.master
|
|
self.rtc_fake.pio = bus.master
|
|
self.flash_fake.pio = bus.master
|
|
self.smcreg_fake.pio = bus.master
|
|
self.energy_ctrl.pio = bus.master
|
|
|
|
# Set the clock domain for IO objects that are considered
|
|
# to be "far" away from the cores.
|
|
def offChipIOClkDomain(self, clkdomain):
|
|
self.uart.clk_domain = clkdomain
|
|
self.realview_io.clk_domain = clkdomain
|
|
self.timer0.clk_domain = clkdomain
|
|
self.timer1.clk_domain = clkdomain
|
|
self.clcd.clk_domain = clkdomain
|
|
self.kmi0.clk_domain = clkdomain
|
|
self.kmi1.clk_domain = clkdomain
|
|
self.dmac_fake.clk_domain = clkdomain
|
|
self.uart1_fake.clk_domain = clkdomain
|
|
self.uart2_fake.clk_domain = clkdomain
|
|
self.uart3_fake.clk_domain = clkdomain
|
|
self.smc_fake.clk_domain = clkdomain
|
|
self.sp810_fake.clk_domain = clkdomain
|
|
self.watchdog_fake.clk_domain = clkdomain
|
|
self.gpio0_fake.clk_domain = clkdomain
|
|
self.gpio1_fake.clk_domain = clkdomain
|
|
self.gpio2_fake.clk_domain = clkdomain
|
|
self.ssp_fake.clk_domain = clkdomain
|
|
self.sci_fake.clk_domain = clkdomain
|
|
self.aaci_fake.clk_domain = clkdomain
|
|
self.mmc_fake.clk_domain = clkdomain
|
|
self.rtc.clk_domain = clkdomain
|
|
self.flash_fake.clk_domain = clkdomain
|
|
self.smcreg_fake.clk_domain = clkdomain
|
|
self.energy_ctrl.clk_domain = clkdomain
|
|
|
|
class VExpress_EMM(RealView):
|
|
_mem_regions = [(Addr('2GB'), Addr('2GB'))]
|
|
pci_cfg_base = 0x30000000
|
|
uart = Pl011(pio_addr=0x1c090000, int_num=37)
|
|
realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000, \
|
|
idreg=0x02250000, pio_addr=0x1C010000)
|
|
gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000)
|
|
local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x2C080000)
|
|
generic_timer = GenericTimer(int_num=29)
|
|
timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C110000, clock0='1MHz', clock1='1MHz')
|
|
timer1 = Sp804(int_num0=35, int_num1=35, pio_addr=0x1C120000, clock0='1MHz', clock1='1MHz')
|
|
clcd = Pl111(pio_addr=0x1c1f0000, int_num=46)
|
|
hdlcd = HDLcd(pio_addr=0x2b000000, int_num=117)
|
|
kmi0 = Pl050(pio_addr=0x1c060000, int_num=44)
|
|
kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, is_mouse=True)
|
|
vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25)
|
|
cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2,
|
|
io_shift = 2, ctrl_offset = 2, Command = 0x1,
|
|
BAR0 = 0x1C1A0000, BAR0Size = '256B',
|
|
BAR1 = 0x1C1A0100, BAR1Size = '4096B',
|
|
BAR0LegacyIO = True, BAR1LegacyIO = True)
|
|
|
|
pciconfig = PciConfigAll(size='256MB')
|
|
vram = SimpleMemory(range = AddrRange(0x18000000, size='32MB'),
|
|
conf_table_reported = False)
|
|
rtc = PL031(pio_addr=0x1C170000, int_num=36)
|
|
|
|
l2x0_fake = IsaFake(pio_addr=0x2C100000, pio_size=0xfff)
|
|
uart1_fake = AmbaFake(pio_addr=0x1C0A0000)
|
|
uart2_fake = AmbaFake(pio_addr=0x1C0B0000)
|
|
uart3_fake = AmbaFake(pio_addr=0x1C0C0000)
|
|
sp810_fake = AmbaFake(pio_addr=0x1C020000, ignore_access=True)
|
|
watchdog_fake = AmbaFake(pio_addr=0x1C0F0000)
|
|
aaci_fake = AmbaFake(pio_addr=0x1C040000)
|
|
lan_fake = IsaFake(pio_addr=0x1A000000, pio_size=0xffff)
|
|
usb_fake = IsaFake(pio_addr=0x1B000000, pio_size=0x1ffff)
|
|
mmc_fake = AmbaFake(pio_addr=0x1c050000)
|
|
energy_ctrl = EnergyCtrl(pio_addr=0x1c080000)
|
|
|
|
# Attach any PCI devices that are supported
|
|
def attachPciDevices(self):
|
|
self.ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0,
|
|
InterruptLine=1, InterruptPin=1)
|
|
self.ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0,
|
|
InterruptLine=2, InterruptPin=2)
|
|
|
|
def enableMSIX(self):
|
|
self.gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000, it_lines=512)
|
|
self.gicv2m = Gicv2m()
|
|
self.gicv2m.frames = [Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2C1C0000)]
|
|
|
|
def setupBootLoader(self, mem_bus, cur_sys, loc):
|
|
self.nvmem = SimpleMemory(range = AddrRange('64MB'),
|
|
conf_table_reported = False)
|
|
self.nvmem.port = mem_bus.master
|
|
cur_sys.boot_loader = loc('boot_emm.arm')
|
|
cur_sys.atags_addr = 0x8000000
|
|
cur_sys.load_addr_mask = 0xfffffff
|
|
cur_sys.load_offset = 0x80000000
|
|
|
|
# Attach I/O devices that are on chip and also set the appropriate
|
|
# ranges for the bridge
|
|
def attachOnChipIO(self, bus, bridge=None):
|
|
self.gic.pio = bus.master
|
|
self.vgic.pio = bus.master
|
|
self.local_cpu_timer.pio = bus.master
|
|
if hasattr(self, "gicv2m"):
|
|
self.gicv2m.pio = bus.master
|
|
self.hdlcd.dma = bus.slave
|
|
if bridge:
|
|
# Bridge ranges based on excluding what is part of on-chip I/O
|
|
# (gic, a9scu)
|
|
bridge.ranges = [AddrRange(0x2F000000, size='16MB'),
|
|
AddrRange(0x2B000000, size='4MB'),
|
|
AddrRange(0x30000000, size='256MB'),
|
|
AddrRange(0x40000000, size='512MB'),
|
|
AddrRange(0x18000000, size='64MB'),
|
|
AddrRange(0x1C000000, size='64MB')]
|
|
|
|
|
|
# Set the clock domain for IO objects that are considered
|
|
# to be "close" to the cores.
|
|
def onChipIOClkDomain(self, clkdomain):
|
|
self.gic.clk_domain = clkdomain
|
|
if hasattr(self, "gicv2m"):
|
|
self.gicv2m.clk_domain = clkdomain
|
|
self.hdlcd.clk_domain = clkdomain
|
|
self.vgic.clk_domain = clkdomain
|
|
|
|
# Attach I/O devices to specified bus object. Done here
|
|
# as the specified bus to connect to may not always be fixed.
|
|
def attachIO(self, bus):
|
|
self.uart.pio = bus.master
|
|
self.realview_io.pio = bus.master
|
|
self.timer0.pio = bus.master
|
|
self.timer1.pio = bus.master
|
|
self.clcd.pio = bus.master
|
|
self.clcd.dma = bus.slave
|
|
self.hdlcd.pio = bus.master
|
|
self.kmi0.pio = bus.master
|
|
self.kmi1.pio = bus.master
|
|
self.cf_ctrl.pio = bus.master
|
|
self.cf_ctrl.dma = bus.slave
|
|
self.cf_ctrl.config = bus.master
|
|
self.rtc.pio = bus.master
|
|
bus.use_default_range = True
|
|
self.vram.port = bus.master
|
|
self.pciconfig.pio = bus.default
|
|
|
|
self.l2x0_fake.pio = bus.master
|
|
self.uart1_fake.pio = bus.master
|
|
self.uart2_fake.pio = bus.master
|
|
self.uart3_fake.pio = bus.master
|
|
self.sp810_fake.pio = bus.master
|
|
self.watchdog_fake.pio = bus.master
|
|
self.aaci_fake.pio = bus.master
|
|
self.lan_fake.pio = bus.master
|
|
self.usb_fake.pio = bus.master
|
|
self.mmc_fake.pio = bus.master
|
|
self.energy_ctrl.pio = bus.master
|
|
|
|
# Try to attach the I/O if it exists
|
|
try:
|
|
self.ide.pio = bus.master
|
|
self.ide.config = bus.master
|
|
self.ide.dma = bus.slave
|
|
self.ethernet.pio = bus.master
|
|
self.ethernet.config = bus.master
|
|
self.ethernet.dma = bus.slave
|
|
except:
|
|
pass
|
|
|
|
# Set the clock domain for IO objects that are considered
|
|
# to be "far" away from the cores.
|
|
def offChipIOClkDomain(self, clkdomain):
|
|
self.uart.clk_domain = clkdomain
|
|
self.realview_io.clk_domain = clkdomain
|
|
self.timer0.clk_domain = clkdomain
|
|
self.timer1.clk_domain = clkdomain
|
|
self.clcd.clk_domain = clkdomain
|
|
self.kmi0.clk_domain = clkdomain
|
|
self.kmi1.clk_domain = clkdomain
|
|
self.cf_ctrl.clk_domain = clkdomain
|
|
self.rtc.clk_domain = clkdomain
|
|
self.vram.clk_domain = clkdomain
|
|
self.pciconfig.clk_domain = clkdomain
|
|
|
|
self.l2x0_fake.clk_domain = clkdomain
|
|
self.uart1_fake.clk_domain = clkdomain
|
|
self.uart2_fake.clk_domain = clkdomain
|
|
self.uart3_fake.clk_domain = clkdomain
|
|
self.sp810_fake.clk_domain = clkdomain
|
|
self.watchdog_fake.clk_domain = clkdomain
|
|
self.aaci_fake.clk_domain = clkdomain
|
|
self.lan_fake.clk_domain = clkdomain
|
|
self.usb_fake.clk_domain = clkdomain
|
|
self.mmc_fake.clk_domain = clkdomain
|
|
self.energy_ctrl.clk_domain = clkdomain
|
|
|
|
class VExpress_EMM64(VExpress_EMM):
|
|
pci_io_base = 0x2f000000
|
|
pci_cfg_gen_offsets = True
|
|
# Three memory regions are specified totalling 512GB
|
|
_mem_regions = [(Addr('2GB'), Addr('2GB')), (Addr('34GB'), Addr('30GB')),
|
|
(Addr('512GB'), Addr('480GB'))]
|
|
def setupBootLoader(self, mem_bus, cur_sys, loc):
|
|
self.nvmem = SimpleMemory(range = AddrRange(0, size = '64MB'))
|
|
self.nvmem.port = mem_bus.master
|
|
cur_sys.boot_loader = loc('boot_emm.arm64')
|
|
cur_sys.atags_addr = 0x8000000
|
|
cur_sys.load_addr_mask = 0xfffffff
|
|
cur_sys.load_offset = 0x80000000
|
|
|
|
|