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This is similar to [1] and [2]. Essentially, the VS bits of STATUS CSR keep track of the state of the vector registers. (VS bits == DIRTY) means the content of vector registers have been updated since the last time the VS bits were updated. This chain of changes is supposed to change the VS bits to DIRTY for if any vector register is potentially updated. [1] https://gem5-review.googlesource.com/c/public/gem5/+/65272 [2] https://github.com/gem5/gem5/pull/370 Change-Id: I0427890dadc63b74a470d7405807dcfcad18005b