1b6355c895
For historical reasons, the ExecContext interface had a single function, readMem(), that did two different things depending on whether the ExecContext supported atomic memory mode (i.e., AtomicSimpleCPU) or timing memory mode (all the other models). In the former case, it actually performed a memory read; in the latter case, it merely initiated a read access, and the read completion did not happen until later when a response packet arrived from the memory system. This led to some confusing things, including timing accesses being required to provide a pointer for the return data even though that pointer was only used in atomic mode. This patch splits this interface, adding a new initiateMemRead() function to the ExecContext interface to replace the timing-mode use of readMem(). For consistency and clarity, the readMemTiming() helper function in the ISA definitions is renamed to initiateMemRead() as well. For x86, where the access size is passed in explicitly, we can also get rid of the data parameter at this level. For other ISAs, where the access size is determined from the type of the data parameter, we have to keep the parameter for that purpose.
419 lines
12 KiB
C++
419 lines
12 KiB
C++
/*
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* Copyright (c) 2014-2015 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Kevin Lim
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* Andreas Sandberg
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* Mitch Hayenga
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*/
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#ifndef __CPU_SIMPLE_EXEC_CONTEXT_HH__
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#define __CPU_SIMPLE_EXEC_CONTEXT_HH__
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#include "arch/registers.hh"
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#include "base/types.hh"
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#include "config/the_isa.hh"
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#include "cpu/base.hh"
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#include "cpu/exec_context.hh"
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#include "cpu/simple/base.hh"
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#include "cpu/static_inst_fwd.hh"
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#include "cpu/translation.hh"
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class BaseSimpleCPU;
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class SimpleExecContext : public ExecContext {
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protected:
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typedef TheISA::MiscReg MiscReg;
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typedef TheISA::FloatReg FloatReg;
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typedef TheISA::FloatRegBits FloatRegBits;
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typedef TheISA::CCReg CCReg;
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public:
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BaseSimpleCPU *cpu;
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SimpleThread* thread;
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// This is the offset from the current pc that fetch should be performed
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Addr fetchOffset;
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// This flag says to stay at the current pc. This is useful for
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// instructions which go beyond MachInst boundaries.
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bool stayAtPC;
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// Branch prediction
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TheISA::PCState predPC;
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/** PER-THREAD STATS */
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// Number of simulated instructions
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Counter numInst;
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Stats::Scalar numInsts;
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Counter numOp;
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Stats::Scalar numOps;
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// Number of integer alu accesses
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Stats::Scalar numIntAluAccesses;
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// Number of float alu accesses
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Stats::Scalar numFpAluAccesses;
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// Number of function calls/returns
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Stats::Scalar numCallsReturns;
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// Conditional control instructions;
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Stats::Scalar numCondCtrlInsts;
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// Number of int instructions
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Stats::Scalar numIntInsts;
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// Number of float instructions
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Stats::Scalar numFpInsts;
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// Number of integer register file accesses
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Stats::Scalar numIntRegReads;
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Stats::Scalar numIntRegWrites;
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// Number of float register file accesses
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Stats::Scalar numFpRegReads;
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Stats::Scalar numFpRegWrites;
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// Number of condition code register file accesses
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Stats::Scalar numCCRegReads;
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Stats::Scalar numCCRegWrites;
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// Number of simulated memory references
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Stats::Scalar numMemRefs;
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Stats::Scalar numLoadInsts;
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Stats::Scalar numStoreInsts;
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// Number of idle cycles
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Stats::Formula numIdleCycles;
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// Number of busy cycles
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Stats::Formula numBusyCycles;
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// Number of simulated loads
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Counter numLoad;
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// Number of idle cycles
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Stats::Average notIdleFraction;
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Stats::Formula idleFraction;
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// Number of cycles stalled for I-cache responses
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Stats::Scalar icacheStallCycles;
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Counter lastIcacheStall;
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// Number of cycles stalled for D-cache responses
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Stats::Scalar dcacheStallCycles;
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Counter lastDcacheStall;
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/// @{
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/// Total number of branches fetched
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Stats::Scalar numBranches;
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/// Number of branches predicted as taken
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Stats::Scalar numPredictedBranches;
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/// Number of misprediced branches
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Stats::Scalar numBranchMispred;
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/// @}
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// Instruction mix histogram by OpClass
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Stats::Vector statExecutedInstType;
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public:
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/** Constructor */
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SimpleExecContext(BaseSimpleCPU* _cpu, SimpleThread* _thread)
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: cpu(_cpu), thread(_thread), fetchOffset(0), stayAtPC(false),
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numInst(0), numOp(0), numLoad(0), lastIcacheStall(0), lastDcacheStall(0)
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{ }
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/** Reads an integer register. */
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IntReg readIntRegOperand(const StaticInst *si, int idx) override
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{
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numIntRegReads++;
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return thread->readIntReg(si->srcRegIdx(idx));
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}
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/** Sets an integer register to a value. */
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void setIntRegOperand(const StaticInst *si, int idx, IntReg val) override
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{
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numIntRegWrites++;
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thread->setIntReg(si->destRegIdx(idx), val);
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}
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/** Reads a floating point register of single register width. */
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FloatReg readFloatRegOperand(const StaticInst *si, int idx) override
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{
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numFpRegReads++;
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int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
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return thread->readFloatReg(reg_idx);
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}
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/** Reads a floating point register in its binary format, instead
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* of by value. */
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FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) override
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{
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numFpRegReads++;
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int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
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return thread->readFloatRegBits(reg_idx);
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}
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/** Sets a floating point register of single width to a value. */
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void setFloatRegOperand(const StaticInst *si, int idx,
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FloatReg val) override
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{
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numFpRegWrites++;
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int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
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thread->setFloatReg(reg_idx, val);
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}
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/** Sets the bits of a floating point register of single width
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* to a binary value. */
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void setFloatRegOperandBits(const StaticInst *si, int idx,
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FloatRegBits val) override
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{
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numFpRegWrites++;
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int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
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thread->setFloatRegBits(reg_idx, val);
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}
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CCReg readCCRegOperand(const StaticInst *si, int idx) override
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{
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numCCRegReads++;
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int reg_idx = si->srcRegIdx(idx) - TheISA::CC_Reg_Base;
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return thread->readCCReg(reg_idx);
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}
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void setCCRegOperand(const StaticInst *si, int idx, CCReg val) override
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{
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numCCRegWrites++;
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int reg_idx = si->destRegIdx(idx) - TheISA::CC_Reg_Base;
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thread->setCCReg(reg_idx, val);
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}
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MiscReg readMiscRegOperand(const StaticInst *si, int idx) override
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{
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numIntRegReads++;
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int reg_idx = si->srcRegIdx(idx) - TheISA::Misc_Reg_Base;
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return thread->readMiscReg(reg_idx);
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}
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void setMiscRegOperand(const StaticInst *si, int idx,
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const MiscReg &val) override
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{
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numIntRegWrites++;
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int reg_idx = si->destRegIdx(idx) - TheISA::Misc_Reg_Base;
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thread->setMiscReg(reg_idx, val);
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}
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/**
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* Reads a miscellaneous register, handling any architectural
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* side effects due to reading that register.
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*/
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MiscReg readMiscReg(int misc_reg) override
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{
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numIntRegReads++;
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return thread->readMiscReg(misc_reg);
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}
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/**
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* Sets a miscellaneous register, handling any architectural
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* side effects due to writing that register.
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*/
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void setMiscReg(int misc_reg, const MiscReg &val) override
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{
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numIntRegWrites++;
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thread->setMiscReg(misc_reg, val);
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}
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PCState pcState() const override
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{
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return thread->pcState();
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}
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void pcState(const PCState &val) override
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{
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thread->pcState(val);
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}
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/**
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* Record the effective address of the instruction.
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*
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* @note Only valid for memory ops.
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*/
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void setEA(Addr EA) override
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{ panic("BaseSimpleCPU::setEA() not implemented\n"); }
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/**
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* Get the effective address of the instruction.
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*
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* @note Only valid for memory ops.
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*/
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Addr getEA() const override
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{ panic("BaseSimpleCPU::getEA() not implemented\n"); }
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Fault readMem(Addr addr, uint8_t *data, unsigned int size,
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unsigned int flags) override
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{
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return cpu->readMem(addr, data, size, flags);
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}
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Fault initiateMemRead(Addr addr, unsigned int size,
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unsigned int flags) override
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{
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return cpu->initiateMemRead(addr, size, flags);
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}
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Fault writeMem(uint8_t *data, unsigned int size, Addr addr,
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unsigned int flags, uint64_t *res) override
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{
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return cpu->writeMem(data, size, addr, flags, res);
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}
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/**
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* Sets the number of consecutive store conditional failures.
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*/
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void setStCondFailures(unsigned int sc_failures) override
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{
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thread->setStCondFailures(sc_failures);
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}
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/**
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* Returns the number of consecutive store conditional failures.
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*/
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unsigned int readStCondFailures() const override
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{
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return thread->readStCondFailures();
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}
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/**
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* Executes a syscall specified by the callnum.
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*/
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void syscall(int64_t callnum) override
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{
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if (FullSystem)
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panic("Syscall emulation isn't available in FS mode.");
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thread->syscall(callnum);
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}
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/** Returns a pointer to the ThreadContext. */
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ThreadContext *tcBase() override
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{
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return thread->getTC();
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}
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/**
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* Somewhat Alpha-specific function that handles returning from an
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* error or interrupt.
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*/
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Fault hwrei() override
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{
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return thread->hwrei();
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}
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/**
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* Check for special simulator handling of specific PAL calls. If
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* return value is false, actual PAL call will be suppressed.
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*/
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bool simPalCheck(int palFunc) override
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{
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return thread->simPalCheck(palFunc);
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}
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bool readPredicate() override
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{
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return thread->readPredicate();
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}
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void setPredicate(bool val) override
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{
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thread->setPredicate(val);
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if (cpu->traceData) {
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cpu->traceData->setPredicate(val);
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}
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}
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/**
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* Invalidate a page in the DTLB <i>and</i> ITLB.
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*/
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void demapPage(Addr vaddr, uint64_t asn) override
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{
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thread->demapPage(vaddr, asn);
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}
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void armMonitor(Addr address) override
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{
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cpu->armMonitor(thread->threadId(), address);
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}
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bool mwait(PacketPtr pkt) override
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{
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return cpu->mwait(thread->threadId(), pkt);
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}
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void mwaitAtomic(ThreadContext *tc) override
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{
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cpu->mwaitAtomic(thread->threadId(), tc, thread->dtb);
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}
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AddressMonitor *getAddrMonitor() override
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{
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return cpu->getCpuAddrMonitor(thread->threadId());
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}
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#if THE_ISA == MIPS_ISA
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MiscReg readRegOtherThread(int regIdx, ThreadID tid = InvalidThreadID)
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override
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{
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panic("Simple CPU models do not support multithreaded "
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"register access.");
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}
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void setRegOtherThread(int regIdx, MiscReg val,
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ThreadID tid = InvalidThreadID) override
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{
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panic("Simple CPU models do not support multithreaded "
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"register access.");
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}
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#endif
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};
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#endif // __CPU_EXEC_CONTEXT_HH__
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