787204c92d
The command executed was `black src configs tests util`. Change-Id: I8dfaa6ab04658fea37618127d6ac19270028d771 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47024 Maintainer: Bobby Bruce <bbruce@ucdavis.edu> Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
92 lines
3.5 KiB
Python
92 lines
3.5 KiB
Python
# Copyright (c) 2012 Mark D. Hill and David A. Wood
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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import m5, os, argparse, sys
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from m5.objects import *
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m5.util.addToPath("../configs/")
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from common.Benchmarks import SysConfig
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from common import FSConfig, SysPaths
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from ruby import Ruby
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from common import Options
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# Add the ruby specific and protocol specific options
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parser = argparse.ArgumentParser()
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Options.addCommonOptions(parser)
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Ruby.define_options(parser)
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args = parser.parse_args()
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# Set the default cache size and associativity to be very small to encourage
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# races between requests and writebacks.
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args.l1d_size = "32kB"
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args.l1i_size = "32kB"
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args.l2_size = "4MB"
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args.l1d_assoc = 2
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args.l1i_assoc = 2
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args.l2_assoc = 2
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args.num_cpus = 2
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# the system
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mdesc = SysConfig(disks=["linux-x86.img"])
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system = FSConfig.makeLinuxX86System(
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"timing", args.num_cpus, mdesc=mdesc, Ruby=True
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)
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system.kernel = SysPaths.binary("x86_64-vmlinux-2.6.22.9")
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# Dummy voltage domain for all our clock domains
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system.voltage_domain = VoltageDomain(voltage=args.sys_voltage)
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system.kernel = FSConfig.binary("x86_64-vmlinux-2.6.22.9.smp")
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system.clk_domain = SrcClockDomain(
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clock="1GHz", voltage_domain=system.voltage_domain
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)
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system.cpu_clk_domain = SrcClockDomain(
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clock="2GHz", voltage_domain=system.voltage_domain
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)
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system.cpu = [
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TimingSimpleCPU(cpu_id=i, clk_domain=system.cpu_clk_domain)
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for i in range(args.num_cpus)
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]
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Ruby.create_system(args, True, system, system.iobus, system._dma_ports)
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# Create a seperate clock domain for Ruby
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system.ruby.clk_domain = SrcClockDomain(
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clock=args.ruby_clock, voltage_domain=system.voltage_domain
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)
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# Connect the ruby io port to the PIO bus,
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# assuming that there is just one such port.
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system.iobus.mem_side_ports = system.ruby._io_port.in_ports
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for (i, cpu) in enumerate(system.cpu):
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# create the interrupt controller
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cpu.createInterruptController()
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# Tie the cpu ports to the correct ruby system ports
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system.ruby._cpu_ports[i].connectCpuPorts(cpu)
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root = Root(full_system=True, system=system)
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m5.ticks.setGlobalFrequency("1THz")
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