Giacomo Travaglini c4ed23a10b arch-arm: Implement HCR_EL2 force broadcast for EL1&0 TLBIs (#1175) ...

According to the Arm architecture reference manual, it is possible to
force the broadcast of the following TLBIs:

AArch64: TLBI VMALLE1, TLBI VAE1, TLBI ASIDE1, TLBI VAAE1, TLBI VALE1,
TLBI VAALE1, IC IALLU, TLBI RVAE1, TLBI RVAAE1, TLBI RVALE1, and TLBI
RVAALE1.

AArch32: BPIALL, TLBIALL, TLBIMVA, TLBIASID, DTLBIALL, DTLBIMVA,
DTLBIASID, ITLBIALL, ITLBIMVA, ITLBIASID, TLBIMVAA, ICIALLU, TLBIMVAL,
and TLBIMVAAL.

Via the HCR_EL2.FB bit

Change-Id: Ib11aa05cd202fadfbd9221db7a2043051196ecbd

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

2024-05-29 11:54:24 +01:00

..

amdgpu

arch-vega: Fix GCC 13 build errors (#1162)

2024-05-28 07:58:28 -07:00

arm

arch-arm: Implement HCR_EL2 force broadcast for EL1&0 TLBIs (#1175)

2024-05-29 11:54:24 +01:00

generic

arch-generic: Avoid out-of-memory errors for bad semihosting calls (#1143)

2024-05-16 10:28:10 -07:00

isa_parser

arch: Fix inst flag of RISC-V vector store macro instructions

2023-12-12 17:04:31 +08:00

mips

misc: Serialize the ISA as a string in the checkpoint

2024-03-04 17:51:40 +00:00

null

scons: Update the Kconfig build options

2023-11-23 08:26:11 +08:00

power

misc: Serialize the ISA as a string in the checkpoint

2024-03-04 17:51:40 +00:00

riscv

arch-riscv: Fix c.jalr and c.jr instruction (#1163)

2024-05-25 20:18:42 -07:00

sparc

arch-riscv,sim: m5ops argument / return fix for 32 bit RISC-V (#900)

2024-04-08 10:09:17 -07:00

x86

arch-x86: Improve KVM set XCR (#1138)

2024-05-20 10:22:48 -07:00

Kconfig

scons: Update the Kconfig build options

2023-11-23 08:26:11 +08:00

micro_asm_test.py

misc: Run pre-commit run --all-files

2023-11-29 22:06:41 -08:00

micro_asm.py

misc: Run pre-commit run --all-files

2023-11-29 22:06:41 -08:00

SConscript

arch-gcn3: Remove all GCN3 files

2024-01-17 10:44:44 -06:00