Gabe Black c4ea43f462 arch-x86: De-indent arch/x86/regs/misc.hh. ...

Namespaces are not supposed to increase indentation.

Change-Id: I6736c5049ea8d853dc67f319192b9eaa97d27cb1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49757
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

2022-06-08 07:08:50 +00:00

..

arch

arch-x86: De-indent arch/x86/regs/misc.hh.

2022-06-08 07:08:50 +00:00

base

misc: Update Dmesg dump for changes to printk in Linux v5.10+.

2022-05-11 13:27:50 +00:00

cpu

cpu: constexpr most of RegId's methods, and add a RegIndex operator.

2022-06-08 07:07:53 +00:00

dev

arch-riscv,dev: Add PCI Host to RISCV Board

2022-06-06 18:42:12 +00:00

doc

misc: Removed unneeded Doxygen pages

2020-04-25 01:08:38 +00:00

doxygen

base,misc: Add group definitions for newly tagged API in src/base

2020-09-08 22:29:43 +00:00

gpu-compute

gpu-compute: Stop passing in a default value to resize().

2022-06-03 10:48:31 +00:00

kern

misc: Update Dmesg dump for changes to printk in Linux v5.10+.

2022-05-11 13:27:50 +00:00

learning_gem5

scons: Add sim_object and enums arguments to SimObject().

2021-12-08 08:01:23 +00:00

mem

mem: Add support for min reads per switch

2022-06-06 18:31:06 +00:00

proto

proto: Add a missing std:: in protoio.cc.

2022-06-03 07:23:27 +00:00

python

stdlib: Add checkpoint to Simulator

2022-06-07 21:18:12 +00:00

sim

sim: Fix erasure ordering in the futex map.

2022-06-03 07:23:18 +00:00

sst

scons: Add sim_object and enums arguments to SimObject().

2021-12-08 08:01:23 +00:00

systemc

systemc: Add SimObject::regStats to systemc kernel

2022-06-06 18:18:10 +00:00

Doxyfile

misc: Revert v21.2 specific commits for develop

2021-12-28 21:30:21 +00:00

SConscript

scons: Update enum output when not using python

2022-05-19 14:32:11 +00:00